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Merge remote-tracking branch 'qmk/master' into merge-2025-02-08

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This commit is contained in:
Ilya Zhuravlev 2025-02-08 20:14:59 -06:00
commit 760225f515
2029 changed files with 49658 additions and 84621 deletions
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84
platforms/arm_atsam/_pin_defs.h
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/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "samd51j18a.h"
#define A00 PIN_PA00
#define A01 PIN_PA01
#define A02 PIN_PA02
#define A03 PIN_PA03
#define A04 PIN_PA04
#define A05 PIN_PA05
#define A06 PIN_PA06
#define A07 PIN_PA07
#define A08 PIN_PA08
#define A09 PIN_PA09
#define A10 PIN_PA10
#define A11 PIN_PA11
#define A12 PIN_PA12
#define A13 PIN_PA13
#define A14 PIN_PA14
#define A15 PIN_PA15
#define A16 PIN_PA16
#define A17 PIN_PA17
#define A18 PIN_PA18
#define A19 PIN_PA19
#define A20 PIN_PA20
#define A21 PIN_PA21
#define A22 PIN_PA22
#define A23 PIN_PA23
#define A24 PIN_PA24
#define A25 PIN_PA25
#define A26 PIN_PA26
#define A27 PIN_PA27
#define A28 PIN_PA28
#define A29 PIN_PA29
#define A30 PIN_PA30
#define A31 PIN_PA31
#define B00 PIN_PB00
#define B01 PIN_PB01
#define B02 PIN_PB02
#define B03 PIN_PB03
#define B04 PIN_PB04
#define B05 PIN_PB05
#define B06 PIN_PB06
#define B07 PIN_PB07
#define B08 PIN_PB08
#define B09 PIN_PB09
#define B10 PIN_PB10
#define B11 PIN_PB11
#define B12 PIN_PB12
#define B13 PIN_PB13
#define B14 PIN_PB14
#define B15 PIN_PB15
#define B16 PIN_PB16
#define B17 PIN_PB17
#define B18 PIN_PB18
#define B19 PIN_PB19
#define B20 PIN_PB20
#define B21 PIN_PB21
#define B22 PIN_PB22
#define B23 PIN_PB23
#define B24 PIN_PB24
#define B25 PIN_PB25
#define B26 PIN_PB26
#define B27 PIN_PB27
#define B28 PIN_PB28
#define B29 PIN_PB29
#define B30 PIN_PB30
#define B31 PIN_PB31

19
platforms/arm_atsam/_timer.h
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/* Copyright 2021 Simon Arlott
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// The platform is 32-bit, so prefer 32-bit timers to avoid overflow
#define FAST_TIMER_T_SIZE 32

9
platforms/arm_atsam/_util.h
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// Copyright 2023 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define RESIDENT_IN_RAM(funcname) __attribute__((section(".ramfunc." #funcname), noinline)) funcname
#if __has_include_next("_util.h")
# include_next "_util.h"
#endif

22
platforms/arm_atsam/_wait.h
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/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "clks.h"
#define wait_ms(ms) CLK_delay_ms(ms)
#define wait_us(us) CLK_delay_us(us)
#define waitInputPinDelay()

37
platforms/arm_atsam/atomic_util.h
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/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "samd51j18a.h"
static __inline__ uint8_t __interrupt_disable__(void) {
__disable_irq();
return 1;
}
static __inline__ void __interrupt_enable__(const uint8_t *__s) {
__enable_irq();
__asm__ volatile("" ::: "memory");
(void)__s;
}
#define ATOMIC_BLOCK(type) for (type, __ToDo = __interrupt_disable__(); __ToDo; __ToDo = 0)
#define ATOMIC_FORCEON uint8_t sreg_save __attribute__((__cleanup__(__interrupt_enable__))) = 0
#define ATOMIC_BLOCK_RESTORESTATE _Static_assert(0, "ATOMIC_BLOCK_RESTORESTATE not implemented")
#define ATOMIC_BLOCK_FORCEON ATOMIC_BLOCK(ATOMIC_FORCEON)

48
platforms/arm_atsam/bootloader.mk
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# Copyright 2017 Jack Humbert
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
# If it's possible that multiple bootloaders can be used for one project,
# you can leave this unset, and the correct size will be selected
# automatically.
#
# Sets the bootloader defined in the keyboard's/keymap's rules.mk
#
# Current options for ARM (ATSAM):
# md-boot Atmel SAM-BA (only used by Drop boards)
#
# If you need to provide your own implementation, you can set inside `rules.mk`
# `BOOTLOADER = custom` -- you'll need to provide your own implementations. See
# the respective file under `platforms/<PLATFORM>/bootloaders/custom.c` to see
# which functions may be overridden.
FIRMWARE_FORMAT?=bin
ifeq ($(strip $(BOOTLOADER)), custom)
OPT_DEFS += -DBOOTLOADER_CUSTOM
BOOTLOADER_TYPE = custom
endif
ifeq ($(strip $(BOOTLOADER)), md-boot)
OPT_DEFS += -DBOOTLOADER_MD_BOOT
BOOTLOADER_TYPE = md_boot
endif
ifeq ($(strip $(BOOTLOADER_TYPE)),)
ifneq ($(strip $(BOOTLOADER)),)
$(call CATASTROPHIC_ERROR,Invalid BOOTLOADER,Invalid bootloader specified. Please set an appropriate bootloader in your rules.mk or info.json.)
else
$(call CATASTROPHIC_ERROR,Invalid BOOTLOADER,No bootloader specified. Please set an appropriate bootloader in your rules.mk or info.json.)
endif
endif

69
platforms/arm_atsam/bootloaders/md_boot.c
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/* Copyright 2017 Fred Sundvik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "bootloader.h"
#include "samd51j18a.h"
// WARNING: These are only for CTRL bootloader release "v2.18Jun 22 2018 17:28:08" for bootloader_jump support
extern uint32_t _eram;
#define BOOTLOADER_MAGIC 0x3B9ACA00
#define MAGIC_ADDR (uint32_t *)((intptr_t)(&_eram) - 4)
// CTRL keyboards released with bootloader version below must use RAM method. Otherwise use WDT method.
void bootloader_jump(void) {
#ifdef KEYBOARD_massdrop_ctrl
uint8_t ver_ram_method[] = "v2.18Jun 22 2018 17:28:08"; // The version to match (NULL terminated by compiler)
uint8_t *ver_check = ver_ram_method; // Pointer to version match string for traversal
uint8_t *ver_rom = (uint8_t *)0x21A0; // Pointer to address in ROM where this specific bootloader version would exist
while (*ver_check && *ver_rom == *ver_check) { // While there are check version characters to match and bootloader's version matches check's version
ver_check++; // Move check version pointer to next character
ver_rom++; // Move ROM version pointer to next character
}
if (!*ver_check) { // If check version pointer is NULL, all characters have matched
*MAGIC_ADDR = BOOTLOADER_MAGIC; // Set magic number into RAM
NVIC_SystemReset(); // Perform system reset
while (1)
; // Won't get here
}
#endif
// Set watchdog timer to reset. Directs the bootloader to stay in programming mode.
WDT->CTRLA.bit.ENABLE = 0;
while (WDT->SYNCBUSY.bit.ENABLE)
;
while (WDT->CTRLA.bit.ENABLE)
;
WDT->CONFIG.bit.WINDOW = 0;
WDT->CONFIG.bit.PER = 0;
WDT->EWCTRL.bit.EWOFFSET = 0;
WDT->CTRLA.bit.ENABLE = 1;
while (WDT->SYNCBUSY.bit.ENABLE)
;
while (!WDT->CTRLA.bit.ENABLE)
;
while (1)
; // Wait on timeout
}
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}

179
platforms/arm_atsam/eeprom_samd.c
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@ -1,179 +0,0 @@
/* Copyright 2017 Fred Sundvik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "eeprom.h"
#include "debug.h"
#include "util.h"
#include "samd51j18a.h"
#include "core_cm4.h"
#include "component/nvmctrl.h"
#include "eeprom_samd.h"
#ifndef BUSY_RETRIES
# define BUSY_RETRIES 10000
#endif
// #define DEBUG_EEPROM_OUTPUT
/*
* Debug print utils
*/
#if defined(DEBUG_EEPROM_OUTPUT)
# define eeprom_printf(fmt, ...) xprintf(fmt, ##__VA_ARGS__);
#else /* NO_DEBUG */
# define eeprom_printf(fmt, ...)
#endif /* NO_DEBUG */
__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE] = {0};
volatile uint8_t * SmartEEPROM8 = (uint8_t *)SEEPROM_ADDR;
static inline bool eeprom_is_busy(void) {
int timeout = BUSY_RETRIES;
while (NVMCTRL->SEESTAT.bit.BUSY && timeout-- > 0)
;
return NVMCTRL->SEESTAT.bit.BUSY;
}
static uint32_t get_virtual_eeprom_size(void) {
// clang-format off
static const uint32_t VIRTUAL_EEPROM_MAP[11][8] = {
/* 4 8 16 32 64 128 256 512 */
/* 0*/ { 0, 0, 0, 0, 0, 0, 0, 0 },
/* 1*/ { 512, 1024, 2048, 4096, 4096, 4096, 4096, 4096 },
/* 2*/ { 512, 1024, 2048, 4096, 8192, 8192, 8192, 8192 },
/* 3*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
/* 4*/ { 512, 1024, 2048, 4096, 8192, 16384, 16384, 16384 },
/* 5*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 6*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 7*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 8*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 32768 },
/* 9*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
/*10*/ { 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 },
};
// clang-format on
static uint32_t virtual_eeprom_size = UINT32_MAX;
if (virtual_eeprom_size == UINT32_MAX) {
virtual_eeprom_size = VIRTUAL_EEPROM_MAP[NVMCTRL->SEESTAT.bit.PSZ][NVMCTRL->SEESTAT.bit.SBLK];
}
// eeprom_printf("get_virtual_eeprom_size:: %d:%d:%d\n", NVMCTRL->SEESTAT.bit.PSZ, NVMCTRL->SEESTAT.bit.SBLK, virtual_eeprom_size);
return virtual_eeprom_size;
}
uint8_t eeprom_read_byte(const uint8_t *addr) {
uintptr_t offset = (uintptr_t)addr;
if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
eeprom_printf("eeprom_read_byte:: out of bounds\n");
return 0x0;
}
if (get_virtual_eeprom_size() == 0) {
return buffer[offset];
}
if (eeprom_is_busy()) {
eeprom_printf("eeprom_write_byte:: timeout\n");
return 0x0;
}
return SmartEEPROM8[offset];
}
void eeprom_write_byte(uint8_t *addr, uint8_t value) {
uintptr_t offset = (uintptr_t)addr;
if (offset >= MAX(EEPROM_SIZE, get_virtual_eeprom_size())) {
eeprom_printf("eeprom_write_byte:: out of bounds\n");
return;
}
if (get_virtual_eeprom_size() == 0) {
buffer[offset] = value;
return;
}
if (eeprom_is_busy()) {
eeprom_printf("eeprom_write_byte:: timeout\n");
return;
}
SmartEEPROM8[offset] = value;
}
uint16_t eeprom_read_word(const uint16_t *addr) {
const uint8_t *p = (const uint8_t *)addr;
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
}
uint32_t eeprom_read_dword(const uint32_t *addr) {
const uint8_t *p = (const uint8_t *)addr;
return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
}
void eeprom_read_block(void *buf, const void *addr, size_t len) {
const uint8_t *p = (const uint8_t *)addr;
uint8_t * dest = (uint8_t *)buf;
while (len--) {
*dest++ = eeprom_read_byte(p++);
}
}
void eeprom_write_word(uint16_t *addr, uint16_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p, value >> 8);
}
void eeprom_write_dword(uint32_t *addr, uint32_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p++, value >> 8);
eeprom_write_byte(p++, value >> 16);
eeprom_write_byte(p, value >> 24);
}
void eeprom_write_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);
}
}
void eeprom_update_byte(uint8_t *addr, uint8_t value) {
eeprom_write_byte(addr, value);
}
void eeprom_update_word(uint16_t *addr, uint16_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p, value >> 8);
}
void eeprom_update_dword(uint32_t *addr, uint32_t value) {
uint8_t *p = (uint8_t *)addr;
eeprom_write_byte(p++, value);
eeprom_write_byte(p++, value >> 8);
eeprom_write_byte(p++, value >> 16);
eeprom_write_byte(p, value >> 24);
}
void eeprom_update_block(const void *buf, void *addr, size_t len) {
uint8_t * p = (uint8_t *)addr;
const uint8_t *src = (const uint8_t *)buf;
while (len--) {
eeprom_write_byte(p++, *src++);
}
}

8
platforms/arm_atsam/eeprom_samd.h
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@ -1,8 +0,0 @@
// Copyright 2022 Nick Brassel (@tzarc)
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#ifndef EEPROM_SIZE
# include "eeconfig.h"
# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
#endif

23
platforms/arm_atsam/flash.mk
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@ -1,23 +0,0 @@
# Hey Emacs, this is a -*- makefile -*-
##############################################################################
# Architecture or project specific options
#
MDLOADER_CLI ?= mdloader
define EXEC_MDLOADER
$(MDLOADER_CLI) --first --download $(BUILD_DIR)/$(TARGET).bin --restart
endef
mdloader: bin
$(call EXEC_MDLOADER)
flash: bin
$(SILENT) || printf "Flashing for bootloader: $(BLUE)$(BOOTLOADER)$(NO_COLOR)\n"
ifneq ($(strip $(PROGRAM_CMD)),)
$(UNSYNC_OUTPUT_CMD) && $(PROGRAM_CMD)
else ifeq ($(strip $(ARM_ATSAM)),SAMD51J18A)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_MDLOADER)
else
$(PRINT_OK); $(SILENT) || printf "$(MSG_FLASH_ARCH)"
endif

81
platforms/arm_atsam/gpio.h
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@ -1,81 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <stdint.h>
#include "samd51j18a.h"
#include "pin_defs.h"
typedef uint8_t pin_t;
#define SAMD_PORT(pin) (((pin)&0x20) >> 5)
#define SAMD_PIN(pin) ((pin)&0x1f)
#define SAMD_PIN_MASK(pin) (1 << ((pin)&0x1f))
#define gpio_set_pin_input(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define gpio_set_pin_input_high(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
} while (0)
#define gpio_set_pin_input_low(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.INEN = 1; \
PORT->Group[SAMD_PORT(pin)].PINCFG[SAMD_PIN(pin)].bit.PULLEN = 1; \
} while (0)
#define gpio_set_pin_output_push_pull(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].DIRSET.reg = SAMD_PIN_MASK(pin); \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define gpio_set_pin_output_open_drain(pin) _Static_assert(0, "Open-drain outputs are not available on ATSAM")
#define gpio_set_pin_output(pin) gpio_set_pin_output_push_pull(pin)
#define gpio_write_pin_high(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define gpio_write_pin_low(pin) \
do { \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define gpio_write_pin(pin, level) \
do { \
if (level) \
PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
else \
PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
} while (0)
#define gpio_read_pin(pin) ((PORT->Group[SAMD_PORT(pin)].IN.reg & SAMD_PIN_MASK(pin)) != 0)
#define gpio_toggle_pin(pin) (PORT->Group[SAMD_PORT(pin)].OUTTGL.reg = SAMD_PIN_MASK(pin))

9
platforms/arm_atsam/hardware_id.c
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@ -1,9 +0,0 @@
// Copyright 2022 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#include "hardware_id.h"
__attribute__((weak)) hardware_id_t get_hardware_id(void) {
hardware_id_t id = {0};
return id;
}

21
platforms/arm_atsam/platform.c
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@ -1,21 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "platform_deps.h"
void platform_setup(void) {
// do nothing
}

68
platforms/arm_atsam/platform.mk
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@ -1,68 +0,0 @@
# Hey Emacs, this is a -*- makefile -*-
##############################################################################
# Compiler settings
#
CC = $(CC_PREFIX) arm-none-eabi-gcc
OBJCOPY = arm-none-eabi-objcopy
OBJDUMP = arm-none-eabi-objdump
SIZE = arm-none-eabi-size
AR = arm-none-eabi-ar
NM = arm-none-eabi-nm
HEX = $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock -R .signature
EEP = $(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT)
BIN =
COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include
COMMON_VPATH += $(LIB_PATH)/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include
COMPILEFLAGS += -funsigned-char
COMPILEFLAGS += -funsigned-bitfields
COMPILEFLAGS += -ffunction-sections
COMPILEFLAGS += -fshort-enums
COMPILEFLAGS += -fno-inline-small-functions
COMPILEFLAGS += -fno-strict-aliasing
COMPILEFLAGS += -mfloat-abi=hard
COMPILEFLAGS += -mfpu=fpv4-sp-d16
COMPILEFLAGS += -mthumb
COMPILEFLAGS += -fno-builtin-printf
#ALLOW_WARNINGS = yes
CFLAGS += $(COMPILEFLAGS)
CXXFLAGS += $(COMPILEFLAGS)
CXXFLAGS += -fno-exceptions $(CXXSTANDARD)
LDFLAGS +=-Wl,--gc-sections
LDFLAGS += -Wl,-Map="%OUT%%PROJ_NAME%.map"
LDFLAGS += -Wl,--start-group
LDFLAGS += -Wl,--end-group
LDFLAGS += --specs=rdimon.specs
LDFLAGS += -T$(LIB_PATH)/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
OPT_DEFS += -DPROTOCOL_ARM_ATSAM
MCUFLAGS = -mcpu=$(MCU)
MCUFLAGS += -D__$(ARM_ATSAM)__
# List any extra directories to look for libraries here.
# Each directory must be seperated by a space.
# Use forward slashes for directory separators.
# For a directory that has spaces, enclose it in quotes.
EXTRALIBDIRS =
cpfirmware: warn-arm_atsam
.INTERMEDIATE: warn-arm_atsam
warn-arm_atsam: $(FIRMWARE_FORMAT)
$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
$(info This MCU support package has a lack of support from the upstream provider (Massdrop).)
$(info There are currently questions about valid licensing, and at this stage it's likely)
$(info their boards and supporting code will be removed from QMK in the near future. Please)
$(info contact Massdrop for support, and encourage them to align their future board design)
$(info choices to gain proper license compatibility with QMK.)
$(info @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)
# Convert hex to bin.
bin: $(BUILD_DIR)/$(TARGET).hex
$(OBJCOPY) -Iihex -Obinary $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
$(COPY) $(BUILD_DIR)/$(TARGET).bin $(TARGET).bin;

18
platforms/arm_atsam/platform_deps.h
View file

@ -1,18 +0,0 @@
/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// here just to please the build

34
platforms/arm_atsam/suspend.c
View file

@ -1,34 +0,0 @@
#include "matrix.h"
#include "i2c_master.h"
#include "md_rgb_matrix.h"
#include "suspend.h"
/** \brief Suspend power down
*
* FIXME: needs doc
*/
void suspend_power_down(void) {
#ifdef RGB_MATRIX_ENABLE
I2C3733_Control_Set(0); // Disable LED driver
#endif
suspend_power_down_kb();
}
/** \brief run immediately after wakeup
*
* FIXME: needs doc
*/
void suspend_wakeup_init(void) {
#ifdef RGB_MATRIX_ENABLE
# ifdef USE_MASSDROP_CONFIGURATOR
if (led_enabled) {
I2C3733_Control_Set(1);
}
# else
I2C3733_Control_Set(1);
# endif
#endif
suspend_wakeup_init_kb();
}

35
platforms/arm_atsam/timer.c
View file

@ -1,35 +0,0 @@
#include "samd51j18a.h"
#include "timer.h"
#include "tmk_core/protocol/arm_atsam/clks.h"
void set_time(uint64_t tset) {
ms_clk = tset;
}
void timer_init(void) {
timer_clear();
}
uint16_t timer_read(void) {
return (uint16_t)ms_clk;
}
uint32_t timer_read32(void) {
return (uint32_t)ms_clk;
}
uint64_t timer_read64(void) {
return ms_clk;
}
uint16_t timer_elapsed(uint16_t tlast) {
return TIMER_DIFF_16(timer_read(), tlast);
}
uint32_t timer_elapsed32(uint32_t tlast) {
return TIMER_DIFF_32(timer_read32(), tlast);
}
void timer_clear(void) {
set_time(0);
}

84
platforms/avr/drivers/spi_master.c
View file

@ -36,9 +36,18 @@
# define SPI_TIMEOUT 100
#endif
static pin_t currentSlavePin = NO_PIN;
static uint8_t currentSlaveConfig = 0;
static bool currentSlave2X = false;
static pin_t current_slave_pin = NO_PIN;
static bool current_cs_active_low = true;
static uint8_t current_slave_config = 0;
static bool current_slave_2x = false;
static inline void spi_select(void) {
gpio_write_pin(current_slave_pin, current_cs_active_low ? 0 : 1);
}
static inline void spi_unselect(void) {
gpio_write_pin(current_slave_pin, current_cs_active_low ? 1 : 0);
}
void spi_init(void) {
gpio_write_pin_high(SPI_SS_PIN);
@ -50,63 +59,74 @@ void spi_init(void) {
}
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
if (currentSlavePin != NO_PIN || slavePin == NO_PIN) {
spi_start_config_t start_config = {0};
start_config.slave_pin = slavePin;
start_config.lsb_first = lsbFirst;
start_config.mode = mode;
start_config.divisor = divisor;
start_config.cs_active_low = true;
return spi_start_extended(&start_config);
}
bool spi_start_extended(spi_start_config_t *start_config) {
if (current_slave_pin != NO_PIN || start_config->slave_pin == NO_PIN) {
return false;
}
currentSlaveConfig = 0;
current_slave_config = 0;
if (lsbFirst) {
currentSlaveConfig |= _BV(DORD);
if (start_config->lsb_first) {
current_slave_config |= _BV(DORD);
}
switch (mode) {
switch (start_config->mode) {
case 1:
currentSlaveConfig |= _BV(CPHA);
current_slave_config |= _BV(CPHA);
break;
case 2:
currentSlaveConfig |= _BV(CPOL);
current_slave_config |= _BV(CPOL);
break;
case 3:
currentSlaveConfig |= (_BV(CPOL) | _BV(CPHA));
current_slave_config |= (_BV(CPOL) | _BV(CPHA));
break;
}
uint16_t roundedDivisor = 1;
while (roundedDivisor < divisor) {
while (roundedDivisor < start_config->divisor) {
roundedDivisor <<= 1;
}
switch (roundedDivisor) {
case 16:
currentSlaveConfig |= _BV(SPR0);
current_slave_config |= _BV(SPR0);
break;
case 64:
currentSlaveConfig |= _BV(SPR1);
current_slave_config |= _BV(SPR1);
break;
case 128:
currentSlaveConfig |= (_BV(SPR1) | _BV(SPR0));
current_slave_config |= (_BV(SPR1) | _BV(SPR0));
break;
case 2:
currentSlave2X = true;
current_slave_2x = true;
break;
case 8:
currentSlave2X = true;
currentSlaveConfig |= _BV(SPR0);
current_slave_2x = true;
current_slave_config |= _BV(SPR0);
break;
case 32:
currentSlave2X = true;
currentSlaveConfig |= _BV(SPR1);
current_slave_2x = true;
current_slave_config |= _BV(SPR1);
break;
}
SPCR |= currentSlaveConfig;
if (currentSlave2X) {
SPCR |= current_slave_config;
if (current_slave_2x) {
SPSR |= _BV(SPI2X);
}
currentSlavePin = slavePin;
gpio_set_pin_output(currentSlavePin);
gpio_write_pin_low(currentSlavePin);
current_slave_pin = start_config->slave_pin;
current_cs_active_low = start_config->cs_active_low;
gpio_set_pin_output(current_slave_pin);
spi_select();
return true;
}
@ -168,13 +188,13 @@ spi_status_t spi_receive(uint8_t *data, uint16_t length) {
}
void spi_stop(void) {
if (currentSlavePin != NO_PIN) {
gpio_set_pin_output(currentSlavePin);
gpio_write_pin_high(currentSlavePin);
currentSlavePin = NO_PIN;
if (current_slave_pin != NO_PIN) {
gpio_set_pin_output(current_slave_pin);
spi_unselect();
current_slave_pin = NO_PIN;
SPSR &= ~(_BV(SPI2X));
SPCR &= ~(currentSlaveConfig);
currentSlaveConfig = 0;
currentSlave2X = false;
SPCR &= ~(current_slave_config);
current_slave_config = 0;
current_slave_2x = false;
}
}

9
platforms/avr/drivers/spi_master.h
View file

@ -41,9 +41,18 @@ typedef int16_t spi_status_t;
#ifdef __cplusplus
extern "C" {
#endif
typedef struct spi_start_config_t {
pin_t slave_pin;
bool lsb_first;
uint8_t mode;
uint16_t divisor;
bool cs_active_low;
} spi_start_config_t;
void spi_init(void);
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
bool spi_start_extended(spi_start_config_t *start_config);
spi_status_t spi_write(uint8_t data);

52
platforms/avr/drivers/ws2812_bitbang.c
View file

@ -28,28 +28,6 @@
#define pinmask(pin) (_BV((pin)&0xF))
/*
* Forward declare internal functions
*
* The functions take a byte-array and send to the data output as WS2812 bitstream.
* The length is the number of bytes to send - three per LED.
*/
static inline void ws2812_sendarray_mask(uint8_t *data, uint16_t datlen, uint8_t masklo, uint8_t maskhi);
void ws2812_init(void) {
DDRx_ADDRESS(WS2812_DI_PIN) |= pinmask(WS2812_DI_PIN);
}
void ws2812_setleds(rgb_led_t *ledarray, uint16_t number_of_leds) {
uint8_t masklo = ~(pinmask(WS2812_DI_PIN)) & PORTx_ADDRESS(WS2812_DI_PIN);
uint8_t maskhi = pinmask(WS2812_DI_PIN) | PORTx_ADDRESS(WS2812_DI_PIN);
ws2812_sendarray_mask((uint8_t *)ledarray, number_of_leds * sizeof(rgb_led_t), masklo, maskhi);
_delay_us(WS2812_TRST_US);
}
/*
This routine writes an array of bytes with RGB values to the Dataout pin
using the fast 800kHz clockless WS2811/2812 protocol.
@ -172,3 +150,33 @@ static inline void ws2812_sendarray_mask(uint8_t *data, uint16_t datlen, uint8_t
SREG = sreg_prev;
}
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_init(void) {
DDRx_ADDRESS(WS2812_DI_PIN) |= pinmask(WS2812_DI_PIN);
}
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
#if defined(WS2812_RGBW)
ws2812_rgb_to_rgbw(&ws2812_leds[index]);
#endif
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
uint8_t masklo = ~(pinmask(WS2812_DI_PIN)) & PORTx_ADDRESS(WS2812_DI_PIN);
uint8_t maskhi = pinmask(WS2812_DI_PIN) | PORTx_ADDRESS(WS2812_DI_PIN);
ws2812_sendarray_mask((uint8_t *)ws2812_leds, WS2812_LED_COUNT * sizeof(ws2812_led_t), masklo, maskhi);
_delay_us(WS2812_TRST_US);
}

22
platforms/avr/drivers/ws2812_i2c.c
View file

@ -1,3 +1,6 @@
// Copyright 2024 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#include "ws2812.h"
#include "i2c_master.h"
@ -13,11 +16,24 @@
# define WS2812_I2C_TIMEOUT 100
#endif
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_init(void) {
i2c_init();
}
// Setleds for standard RGB
void ws2812_setleds(rgb_led_t *ledarray, uint16_t leds) {
i2c_transmit(WS2812_I2C_ADDRESS, (uint8_t *)ledarray, sizeof(rgb_led_t) * leds, WS2812_I2C_TIMEOUT);
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
i2c_transmit(WS2812_I2C_ADDRESS, (uint8_t *)ws2812_leds, WS2812_LED_COUNT * sizeof(ws2812_led_t), WS2812_I2C_TIMEOUT);
}

19
platforms/avr/timer.c
View file

@ -25,6 +25,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
// counter resolution 1ms
// NOTE: union { uint32_t timer32; struct { uint16_t dummy; uint16_t timer16; }}
volatile uint32_t timer_count;
static uint32_t saved_ms;
/** \brief timer initialization
*
@ -78,6 +79,24 @@ inline void timer_clear(void) {
}
}
/** \brief timer save
*
* Set saved_ms to current time.
*/
void timer_save(void) {
saved_ms = timer_read32();
}
/** \brief timer restore
*
* Set timer_count to saved_ms
*/
void timer_restore(void) {
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
timer_count = saved_ms;
}
}
/** \brief timer read
*
* FIXME: needs doc

101
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c Normal file
View file

@ -0,0 +1,101 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2023..2024 HorrorTroll
ChibiOS - Copyright (C) 2023..2024 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config =
{
{VAL_GPIOAODT, VAL_GPIOACFGLR, VAL_GPIOACFGHR},
{VAL_GPIOBODT, VAL_GPIOBCFGLR, VAL_GPIOBCFGHR},
#if AT32_HAS_GPIOC
{VAL_GPIOCODT, VAL_GPIOCCFGLR, VAL_GPIOCCFGHR},
#endif
{VAL_GPIODODT, VAL_GPIODCFGLR, VAL_GPIODCFGHR},
#if AT32_HAS_GPIOF
{VAL_GPIOFODT, VAL_GPIOFCFGLR, VAL_GPIOFCFGHR},
#endif
};
#endif
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details System clocks are initialized before everything else.
*/
void __early_init(void) {
at32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
static bool last_status = false;
if (blkIsTransferring(sdcp))
return last_status;
return last_status = (bool)palReadPad(GPIOC, GPIOC_PIN11);
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return false;
}
#endif /* HAL_USE_SDC */
/**
* @brief Board-specific initialization code.
* @note You can add your board-specific code here.
*/
void boardInit(void) {
IOMUX->REMAP |= IOMUX_REMAP_SWJTAG_MUX_JTAGDIS;
}

207
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h Normal file
View file

@ -0,0 +1,207 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2023..2024 HorrorTroll
ChibiOS - Copyright (C) 2023..2024 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*
* Setup for a Generic AT32F415 board.
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_AT32_F415XX
#define BOARD_NAME "GENERIC AT32F415 board"
/*
* Board oscillators-related settings.
*/
#if !defined(AT32_LEXTCLK)
#define AT32_LEXTCLK 32768
#endif
#if !defined(AT32_HEXTCLK)
#define AT32_HEXTCLK 8000000
#endif
/*
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
*/
#define AT32F415KB
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_HEXT_IN 0U
#define GPIOD_HEXT_OUT 1U
#define GPIOD_PIN2 2U
#define GPIOF_PIN4 4U
#define GPIOF_PIN5 5U
#define GPIOF_PIN6 6U
#define GPIOF_PIN7 7U
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
*
* The digits have the following meaning:
* 0 - Analog input.
* 1 - Push Pull output 10MHz.
* 2 - Push Pull output 2MHz.
* 3 - Push Pull output 50MHz.
* 4 - Digital input.
* 5 - Open Drain output 10MHz.
* 6 - Open Drain output 2MHz.
* 7 - Open Drain output 50MHz.
* 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT.
* 9 - Alternate Push Pull output 10MHz.
* A - Alternate Push Pull output 2MHz.
* B - Alternate Push Pull output 50MHz.
* C - Reserved.
* D - Alternate Open Drain output 10MHz.
* E - Alternate Open Drain output 2MHz.
* F - Alternate Open Drain output 50MHz.
* Please refer to the AT32 Reference Manual for details.
*/
/*
* Port A setup.
*/
#define VAL_GPIOACFGLR 0x88888B88 /* PA7...PA0 */
#define VAL_GPIOACFGHR 0x888888B8 /* PA15...PA8 */
#define VAL_GPIOAODT 0xFFFFFFFF
/*
* Port B setup.
*/
#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */
#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */
#define VAL_GPIOBODT 0xFFFFFFFF
/*
* Port C setup.
*/
#define VAL_GPIOCCFGLR 0x88888888 /* PC7...PC0 */
#define VAL_GPIOCCFGHR 0x88888888 /* PC15...PC8 */
#define VAL_GPIOCODT 0xFFFFFFFF
/*
* Port D setup.
* Everything input with pull-up except:
* PD0 - Normal input (GPIOD_HEXT_IN).
* PD1 - Normal input (GPIOD_HEXT_OUT).
*/
#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */
#define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */
#define VAL_GPIODODT 0xFFFFFFFF
/*
* Port F setup.
*/
#define VAL_GPIOFCFGLR 0x88888888 /* PF7...PF0 */
#define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */
#define VAL_GPIOFODT 0xFFFFFFFF
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

9
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.mk Normal file
View file

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(BOARD_PATH)/board/board.c
# Required include directories
BOARDINC = $(BOARD_PATH)/board
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

13
platforms/chibios/boards/GENERIC_AT32_F415XX/configs/config.h Normal file
View file

@ -0,0 +1,13 @@
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll>
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12>
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#define BOARD_OTG_VBUSIG
#define USB_ENDPOINTS_ARE_REORDERABLE
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif

236
platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h Normal file
View file

@ -0,0 +1,236 @@
/*
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
ChibiOS - Copyright (C) 2023..2024 HorrorTroll
ChibiOS - Copyright (C) 2023..2024 Zhaqian
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* AT32F415 drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define AT32F415_MCUCONF
/*
* General settings.
*/
#define AT32_NO_INIT FALSE
/*
* HAL driver system settings.
*/
#define AT32_HICK_ENABLED TRUE
#define AT32_LICK_ENABLED FALSE
#define AT32_HEXT_ENABLED TRUE
#define AT32_LEXT_ENABLED FALSE
#define AT32_SCLKSEL AT32_SCLKSEL_PLL
#define AT32_PLLRCS AT32_PLLRCS_HEXT
#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1
#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID
#define AT32_PLLMULT_VALUE 18
#define AT32_PLL_FR_VALUE 4
#define AT32_PLL_MS_VALUE 1
#define AT32_PLL_NS_VALUE 72
#define AT32_AHBDIV AT32_AHBDIV_DIV1
#define AT32_APB1DIV AT32_APB1DIV_DIV2
#define AT32_APB2DIV AT32_APB2DIV_DIV2
#define AT32_ADCDIV AT32_ADCDIV_DIV4
#define AT32_USB_CLOCK_REQUIRED TRUE
#define AT32_USBDIV AT32_USBDIV_DIV3
#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK
#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1
#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV
#define AT32_PVM_ENABLE FALSE
#define AT32_PVMSEL AT32_PVMSEL_LEV1
/*
* IRQ system settings.
*/
#define AT32_IRQ_EXINT0_PRIORITY 6
#define AT32_IRQ_EXINT1_PRIORITY 6
#define AT32_IRQ_EXINT2_PRIORITY 6
#define AT32_IRQ_EXINT3_PRIORITY 6
#define AT32_IRQ_EXINT4_PRIORITY 6
#define AT32_IRQ_EXINT5_9_PRIORITY 6
#define AT32_IRQ_EXINT10_15_PRIORITY 6
#define AT32_IRQ_EXINT16_PRIORITY 6
#define AT32_IRQ_EXINT17_PRIORITY 15
#define AT32_IRQ_EXINT18_PRIORITY 6
#define AT32_IRQ_EXINT19_PRIORITY 6
#define AT32_IRQ_EXINT20_PRIORITY 6
#define AT32_IRQ_EXINT21_PRIORITY 15
#define AT32_IRQ_EXINT22_PRIORITY 15
#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7
#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7
#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7
#define AT32_IRQ_TMR1_CH_PRIORITY 7
#define AT32_IRQ_TMR2_PRIORITY 7
#define AT32_IRQ_TMR3_PRIORITY 7
#define AT32_IRQ_TMR4_PRIORITY 7
#define AT32_IRQ_TMR5_PRIORITY 7
#define AT32_IRQ_USART1_PRIORITY 12
#define AT32_IRQ_USART2_PRIORITY 12
#define AT32_IRQ_USART3_PRIORITY 12
#define AT32_IRQ_UART4_PRIORITY 12
#define AT32_IRQ_UART5_PRIORITY 12
/*
* ADC driver system settings.
*/
#define AT32_ADC_USE_ADC1 FALSE
#define AT32_ADC_ADC1_DMA_PRIORITY 2
#define AT32_ADC_ADC1_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define AT32_CAN_USE_CAN1 FALSE
#define AT32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DMA driver system settings.
*/
#define AT32_DMA_USE_DMAMUX TRUE
/*
* GPT driver system settings.
*/
#define AT32_GPT_USE_TMR1 FALSE
#define AT32_GPT_USE_TMR2 FALSE
#define AT32_GPT_USE_TMR3 FALSE
#define AT32_GPT_USE_TMR4 FALSE
#define AT32_GPT_USE_TMR5 FALSE
#define AT32_GPT_USE_TMR9 FALSE
#define AT32_GPT_USE_TMR10 FALSE
#define AT32_GPT_USE_TMR11 FALSE
/*
* I2C driver system settings.
*/
#define AT32_I2C_USE_I2C1 FALSE
#define AT32_I2C_USE_I2C2 FALSE
#define AT32_I2C_BUSY_TIMEOUT 50
#define AT32_I2C_I2C1_IRQ_PRIORITY 5
#define AT32_I2C_I2C2_IRQ_PRIORITY 5
#define AT32_I2C_I2C1_DMA_PRIORITY 3
#define AT32_I2C_I2C2_DMA_PRIORITY 3
#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define AT32_ICU_USE_TMR1 FALSE
#define AT32_ICU_USE_TMR2 FALSE
#define AT32_ICU_USE_TMR3 FALSE
#define AT32_ICU_USE_TMR4 FALSE
#define AT32_ICU_USE_TMR5 FALSE
#define AT32_ICU_USE_TMR9 FALSE
#define AT32_ICU_USE_TMR10 FALSE
#define AT32_ICU_USE_TMR11 FALSE
/*
* PWM driver system settings.
*/
#define AT32_PWM_USE_TMR1 FALSE
#define AT32_PWM_USE_TMR2 FALSE
#define AT32_PWM_USE_TMR3 FALSE
#define AT32_PWM_USE_TMR4 FALSE
#define AT32_PWM_USE_TMR5 FALSE
#define AT32_PWM_USE_TMR9 FALSE
#define AT32_PWM_USE_TMR10 FALSE
#define AT32_PWM_USE_TMR11 FALSE
/*
* RTC driver system settings.
*/
#define AT32_ERTC_DIVA_VALUE 32
#define AT32_ERTC_DIVB_VALUE 1024
#define AT32_ERTC_CTRL_INIT 0
#define AT32_ERTC_TAMP_INIT 0
/*
* SDC driver system settings.
*/
#define AT32_SDC_SDIO_DMA_PRIORITY 3
#define AT32_SDC_SDIO_IRQ_PRIORITY 9
#define AT32_SDC_WRITE_TIMEOUT_MS 1000
#define AT32_SDC_READ_TIMEOUT_MS 1000
#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10
#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
/*
* SERIAL driver system settings.
*/
#define AT32_SERIAL_USE_USART1 FALSE
#define AT32_SERIAL_USE_USART2 FALSE
#define AT32_SERIAL_USE_USART3 FALSE
#define AT32_SERIAL_USE_UART4 FALSE
#define AT32_SERIAL_USE_UART5 FALSE
/*
* SPI driver system settings.
*/
#define AT32_SPI_USE_SPI1 FALSE
#define AT32_SPI_USE_SPI2 FALSE
#define AT32_SPI_SPI1_DMA_PRIORITY 1
#define AT32_SPI_SPI2_DMA_PRIORITY 1
#define AT32_SPI_SPI1_IRQ_PRIORITY 10
#define AT32_SPI_SPI2_IRQ_PRIORITY 10
#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define AT32_ST_IRQ_PRIORITY 8
#define AT32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define AT32_UART_USE_USART1 FALSE
#define AT32_UART_USE_USART2 FALSE
#define AT32_UART_USE_USART3 FALSE
#define AT32_UART_USART1_DMA_PRIORITY 0
#define AT32_UART_USART2_DMA_PRIORITY 0
#define AT32_UART_USART3_DMA_PRIORITY 0
#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define AT32_USB_USE_OTG1 TRUE
#define AT32_USB_OTG1_IRQ_PRIORITY 14
#define AT32_USB_OTG1_RX_FIFO_SIZE 512
/*
* WDG driver system settings.
*/
#define AT32_WDG_USE_WDT FALSE
#endif /* MCUCONF_H */

10
platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
View file

@ -21,3 +21,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

10
platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
View file

@ -21,3 +21,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

10
platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
View file

@ -17,3 +17,13 @@
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
#ifdef WEAR_LEVELING_EMBEDDED_FLASH
# ifndef WEAR_LEVELING_EFL_FIRST_SECTOR
# ifdef BOOTLOADER_TINYUF2
# define WEAR_LEVELING_EFL_FIRST_SECTOR 3
# else
# define WEAR_LEVELING_EFL_FIRST_SECTOR 1
# endif
# endif
#endif

2
platforms/chibios/boards/GENERIC_STM32_L433XC/configs/mcuconf.h
View file

@ -40,7 +40,7 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI16_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_MSIPLL_ENABLED FALSE

90
platforms/chibios/boards/common/ld/STM32F401xC.ld
View file

@ -1,85 +1,13 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xC memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 256k - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 64k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 256k;
f4xx_ram1_size = 64k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
INCLUDE stm32f4xx_common.ld

93
platforms/chibios/boards/common/ld/STM32F401xC_tinyuf2.ld
View file

@ -1,88 +1,13 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xC memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 64k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 256k;
f4xx_ram1_size = 64k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
INCLUDE stm32f4xx_tinyuf2_common.ld

90
platforms/chibios/boards/common/ld/STM32F401xE.ld
View file

@ -1,85 +1,13 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xE memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 96k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 96k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
INCLUDE stm32f4xx_common.ld

93
platforms/chibios/boards/common/ld/STM32F401xE_tinyuf2.ld
View file

@ -1,88 +1,13 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F401xE memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = 512k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 96k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 96k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F405xG memory setup.
* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 1M;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 64k;
f4xx_ram5_size = 4k;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
INCLUDE stm32f4xx_common.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F405xG memory setup.
* Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = 1M - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */
ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 1M;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 64k;
f4xx_ram5_size = 4k;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 64k;
f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_common.ld

13
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/*
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 64k;
f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
f4xx_flash_size = 256k;
f4xx_ram1_size = 128k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
INCLUDE stm32f4xx_common.ld

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@ -1,89 +1,13 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F411xC memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = 256k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
f4xx_flash_size = 256k;
f4xx_ram1_size = 128k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F411xE memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 128k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
INCLUDE stm32f4xx_common.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F411xE memory setup.
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = 512k - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 128k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */
f4xx_flash_size = 512k;
f4xx_ram1_size = 128k;
f4xx_ram2_size = 0;
f4xx_ram4_size = 0;
f4xx_ram5_size = 0;
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 0;
f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_common.ld

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/*
* Copyright 2006..2018 Giovanni Di Sirio
* Copyright 2022 QMK contributors
* SPDX-License-Identifier: GPL-2.0-or-later
*/
f4xx_flash_size = 512k;
f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k;
f4xx_ram4_size = 0;
f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_tinyuf2_common.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */
flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */
flash2 (rx) : org = 0x08008000, len = f4xx_flash_size - 32k /* Sector 2..6 - Rest of firmware */
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash2);
REGION_ALIAS("XTORS_FLASH_LMA", flash2);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash2);
REGION_ALIAS("TEXT_FLASH_LMA", flash2);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash2);
REGION_ALIAS("RODATA_FLASH_LMA", flash2);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash2);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash2);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

88
platforms/chibios/boards/common/ld/stm32f4xx_tinyuf2_common.ld Normal file
View file

@ -0,0 +1,88 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F411xE memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000 + 64k, len = f4xx_flash_size - 64k /* tinyuf2 bootloader requires app to be located at 64k offset for this MCU */
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k - 4; /* this is based off the linker file for tinyuf2 */

9
platforms/chibios/bootloader.mk
View file

@ -26,6 +26,7 @@
# stm32-dfu STM32 USB DFU in ROM
# apm32-dfu APM32 USB DFU in ROM
# wb32-dfu WB32 USB DFU in ROM
# at32-dfu AT32 USB DFU in ROM
# tinyuf2 TinyUF2
# rp2040 Raspberry Pi RP2040
# Current options for RISC-V:
@ -130,6 +131,14 @@ ifeq ($(strip $(BOOTLOADER)), wb32-dfu)
OPT_DEFS += -DBOOTLOADER_WB32_DFU
BOOTLOADER_TYPE = wb32_dfu
endif
ifeq ($(strip $(BOOTLOADER)), at32-dfu)
OPT_DEFS += -DBOOTLOADER_AT32_DFU
BOOTLOADER_TYPE = at32_dfu
# Options to pass to dfu-util when flashing
DFU_ARGS ?= -d 2E3C:DF11 -a 0 -s 0x08000000:leave
DFU_SUFFIX_ARGS ?= -v 2E3C -p DF11
endif
ifeq ($(strip $(BOOTLOADER_TYPE)),)
ifneq ($(strip $(BOOTLOADER)),)

83
platforms/chibios/bootloaders/at32_dfu.c Normal file
View file

@ -0,0 +1,83 @@
// Copyright 2021-2023 QMK
// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll>
// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12>
// SPDX-License-Identifier: GPL-2.0-or-later
#include "bootloader.h"
#include "util.h"
#include <ch.h>
#include <hal.h>
#include "wait.h"
#ifndef AT32_BOOTLOADER_RAM_SYMBOL
# define AT32_BOOTLOADER_RAM_SYMBOL __ram0_end__
#endif
extern uint32_t AT32_BOOTLOADER_RAM_SYMBOL;
/* This code should be checked whether it runs correctly on platforms */
#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
#define BOOTLOADER_MAGIC 0xDEADBEEF
#define MAGIC_ADDR (unsigned long *)(SYMVAL(AT32_BOOTLOADER_RAM_SYMBOL) - 4)
__attribute__((weak)) void bootloader_marker_enable(void) {
uint32_t *marker = (uint32_t *)MAGIC_ADDR;
*marker = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
}
__attribute__((weak)) bool bootloader_marker_active(void) {
const uint32_t *marker = (const uint32_t *)MAGIC_ADDR;
return (*marker == BOOTLOADER_MAGIC) ? true : false;
}
__attribute__((weak)) void bootloader_marker_disable(void) {
uint32_t *marker = (uint32_t *)MAGIC_ADDR;
*marker = 0;
}
__attribute__((weak)) void bootloader_jump(void) {
bootloader_marker_enable();
NVIC_SystemReset();
}
__attribute__((weak)) void mcu_reset(void) {
NVIC_SystemReset();
}
void enter_bootloader_mode_if_requested(void) {
if (bootloader_marker_active()) {
bootloader_marker_disable();
struct system_memory_vector_t {
uint32_t stack_top;
void (*entrypoint)(void);
};
const struct system_memory_vector_t *bootloader = (const struct system_memory_vector_t *)(AT32_BOOTLOADER_ADDRESS);
__disable_irq();
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
ARM_MPU_Disable();
#endif
SysTick->CTRL = 0;
SysTick->VAL = 0;
SysTick->LOAD = 0;
// Clear interrupt enable and interrupt pending registers
for (int i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
NVIC->ICER[i] = 0xFFFFFFFF;
NVIC->ICPR[i] = 0xFFFFFFFF;
}
__set_CONTROL(0);
__set_MSP(bootloader->stack_top);
__enable_irq();
// Jump to bootloader
bootloader->entrypoint();
while (true) {
}
}
}

13
platforms/chibios/chibios_config.h
View file

@ -142,6 +142,19 @@
# endif
#endif
// AT32 compatibility
#if defined(MCU_AT32)
# define CPU_CLOCK AT32_SYSCLK
# if defined(AT32F415)
# define USE_GPIOV1
# define USE_I2CV1
# define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_AT32_ALTERNATE_OPENDRAIN
# define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_AT32_ALTERNATE_PUSHPULL
# define AUDIO_PWM_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL
# endif
#endif
#if defined(GD32VF103)
/* This chip has the same API as STM32F103, but uses different names for literally the same thing.
* As of 4.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake

4
platforms/chibios/config.h
View file

@ -5,3 +5,7 @@
#ifndef CORTEX_ENABLE_WFI_IDLE
# define CORTEX_ENABLE_WFI_IDLE TRUE
#endif // CORTEX_ENABLE_WFI_IDLE
#ifndef SERIAL_NUMBER_USE_HARDWARE_ID
# define SERIAL_NUMBER_USE_HARDWARE_ID TRUE
#endif // SERIAL_NUMBER_USE_HARDWARE_ID

36
platforms/chibios/converters/promicro_to_svlinky/_pin_defs.h Normal file
View file

@ -0,0 +1,36 @@
// Copyright 2023 QMK
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
// Left side (front)
#define D3 0U
#define D2 1U
// GND
// GND
#define D1 2U
#define D0 3U
#define D4 4U
#define C6 5U
#define D7 6U
#define E6 7U
#define B4 8U
#define B5 9U
// Right side (front)
// RAW
// GND
// RESET
// VCC
#define F4 29U
#define F5 28U
#define F6 18U
#define F7 24U
#define B1 22U
#define B3 20U
#define B2 23U
#define B6 21U
// LEDs
#define D5 17U
#define B0 25U

10
platforms/chibios/converters/promicro_to_svlinky/converter.mk Normal file
View file

@ -0,0 +1,10 @@
# rp2040_ce MCU settings for converting AVR projects
MCU := RP2040
BOARD := QMK_PM2040
BOOTLOADER := rp2040
# These are defaults based on what has been implemented for RP2040 boards
SERIAL_DRIVER ?= vendor
WS2812_DRIVER ?= vendor
BACKLIGHT_DRIVER ?= software
OPT_DEFS += -DUSB_VBUS_PIN=19U

23
platforms/chibios/drivers/analog.c
View file

@ -22,7 +22,7 @@
# error "You need to set HAL_USE_ADC to TRUE in your halconf.h to use the ADC."
#endif
#if !RP_ADC_USE_ADC1 && !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 && !WB32_ADC_USE_ADC1
#if !RP_ADC_USE_ADC1 && !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 && !WB32_ADC_USE_ADC1 && !AT32_ADC_USE_ADC1
# error "You need to set one of the 'xxx_ADC_USE_ADCx' settings to TRUE in your mcuconf.h to use the ADC."
#endif
@ -45,7 +45,7 @@
// Otherwise assume V3
#if defined(STM32F0XX) || defined(STM32L0XX)
# define USE_ADCV1
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define USE_ADCV2
#endif
@ -82,7 +82,7 @@
/* User configurable ADC options */
#ifndef ADC_COUNT
# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define ADC_COUNT 1
# elif defined(STM32F3XX) || defined(STM32G4XX)
# define ADC_COUNT 4
@ -142,11 +142,16 @@ static ADCConversionGroup adcConversionGroup = {
.cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
.smpr = ADC_SAMPLING_RATE,
#elif defined(USE_ADCV2)
# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx)
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx) && !defined(AT32F415)
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
# endif
# if defined(AT32F415)
.spt2 = ADC_SPT2_CSPT_AN0(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN1(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN2(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN3(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN4(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN5(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN6(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN7(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN8(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN9(ADC_SAMPLING_RATE),
.spt1 = ADC_SPT1_CSPT_AN10(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN11(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN12(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN13(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN14(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN15(ADC_SAMPLING_RATE),
# else
.smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
.smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
# endif
#elif defined(RP2040)
// RP2040 does not have any extra config here
#else
@ -242,7 +247,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
# endif
#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
@ -344,7 +349,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) {
static inline ADCDriver* intToADCDriver(uint8_t adcInt) {
switch (adcInt) {
#if RP_ADC_USE_ADC1 || STM32_ADC_USE_ADC1 || WB32_ADC_USE_ADC1
#if RP_ADC_USE_ADC1 || STM32_ADC_USE_ADC1 || WB32_ADC_USE_ADC1 || AT32_ADC_USE_ADC1
case 0:
return &ADCD1;
#endif
@ -391,7 +396,11 @@ int16_t adc_read(adc_mux mux) {
// TODO: fix previous assumption of only 1 input...
adcConversionGroup.chselr = 1 << mux.input; /*no macro to convert N to ADC_CHSELR_CHSEL1*/
#elif defined(USE_ADCV2)
# if defined(AT32F415)
adcConversionGroup.osq3 = ADC_OSQ3_OSN1_N(mux.input);
# else
adcConversionGroup.sqr3 = ADC_SQR3_SQ1_N(mux.input);
# endif
#elif defined(RP2040)
adcConversionGroup.channel_mask = 1 << mux.input;
#else

2
platforms/chibios/drivers/backlight_pwm.c
View file

@ -25,7 +25,7 @@
# define BACKLIGHT_PWM_CHANNEL 3
#endif
// Support for pins which are on TIM1_CH1N - requires STM32_PWM_USE_ADVANCED
// Support for pins which are on TIM1_CH1N
#ifdef BACKLIGHT_PWM_COMPLEMENTARY_OUTPUT
# if BACKLIGHT_ON_STATE == 1
# define PWM_OUTPUT_MODE PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW;

4
platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.h
View file

@ -27,7 +27,3 @@
# define STM32_ONBOARD_EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO and EEPROM page sizing
# endif
#endif
#if STM32_ONBOARD_EEPROM_SIZE > 128
# pragma message("Please note: resetting EEPROM using an STM32L0/L1 device takes up to 1 second for every 1kB of internal EEPROM used.")
#endif

15
platforms/chibios/drivers/serial_usart.c
View file

@ -9,6 +9,17 @@
#if defined(SERIAL_USART_CONFIG)
static QMKSerialConfig serial_config = SERIAL_USART_CONFIG;
#elif defined(MCU_AT32) /* AT32 MCUs */
static QMKSerialConfig serial_config = {
.speed = (SERIAL_USART_SPEED),
.ctrl1 = (SERIAL_USART_CTRL1),
.ctrl2 = (SERIAL_USART_CTRL2),
# if !defined(SERIAL_USART_FULL_DUPLEX)
.ctrl3 = ((SERIAL_USART_CTRL3) | USART_CTRL3_SLBEN) /* activate half-duplex mode */
# else
.ctrl3 = (SERIAL_USART_CTRL3)
# endif
};
#elif defined(MCU_STM32) /* STM32 MCUs */
static QMKSerialConfig serial_config = {
# if HAL_USE_SERIAL
@ -160,7 +171,7 @@ inline bool serial_transport_receive_blocking(uint8_t* destination, const size_t
* @brief Initiate pins for USART peripheral. Half-duplex configuration.
*/
__attribute__((weak)) void usart_init(void) {
# if defined(MCU_STM32) /* STM32 MCUs */
# if defined(MCU_STM32) || defined(MCU_AT32) /* STM32 and AT32 MCUs */
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_OPENDRAIN);
# else
@ -183,7 +194,7 @@ __attribute__((weak)) void usart_init(void) {
* @brief Initiate pins for USART peripheral. Full-duplex configuration.
*/
__attribute__((weak)) void usart_init(void) {
# if defined(MCU_STM32) /* STM32 MCUs */
# if defined(MCU_STM32) || defined(MCU_AT32) /* STM32 and AT32 MCUs */
# if defined(USE_GPIOV1)
palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE_PUSHPULL);
palSetLineMode(SERIAL_USART_RX_PIN, PAL_MODE_INPUT);

99
platforms/chibios/drivers/serial_usart.h
View file

@ -74,40 +74,75 @@ typedef SIOConfig QMKSerialConfig;
# endif
#endif
#if !defined(USART_CR1_M0)
# define USART_CR1_M0 USART_CR1_M // some platforms (f1xx) dont have this so
#endif
#if defined(MCU_STM32) /* STM32 MCUs */
# if !defined(USART_CR1_M0)
# define USART_CR1_M0 USART_CR1_M // some platforms (f1xx) dont have this so
# endif
#if !defined(SERIAL_USART_CR1)
# define SERIAL_USART_CR1 (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0) // parity enable, odd parity, 9 bit length
#endif
# if !defined(SERIAL_USART_CR1)
# define SERIAL_USART_CR1 (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0) // parity enable, odd parity, 9 bit length
# endif
#if !defined(SERIAL_USART_CR2)
# define SERIAL_USART_CR2 (USART_CR2_STOP_1) // 2 stop bits
#endif
# if !defined(SERIAL_USART_CR2)
# define SERIAL_USART_CR2 (USART_CR2_STOP_1) // 2 stop bits
# endif
#if !defined(SERIAL_USART_CR3)
# define SERIAL_USART_CR3 0
#endif
# if !defined(SERIAL_USART_CR3)
# define SERIAL_USART_CR3 0
# endif
#if defined(USART1_REMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART1_REMAP); \
} while (0)
#elif defined(USART2_REMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART2_REMAP); \
} while (0)
#elif defined(USART3_PARTIALREMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
} while (0)
#elif defined(USART3_FULLREMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP); \
} while (0)
# if defined(USART1_REMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART1_REMAP); \
} while (0)
# elif defined(USART2_REMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART2_REMAP); \
} while (0)
# elif defined(USART3_PARTIALREMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
} while (0)
# elif defined(USART3_FULLREMAP)
# define USART_REMAP \
do { \
(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP); \
} while (0)
# endif
#elif defined(MCU_AT32) /* AT32 MCUs */
# if !defined(USART_CTRL1_DBN0)
# define USART_CTRL1_DBN0 USART_CTRL1_DBN
# endif
# if !defined(SERIAL_USART_CTRL1)
# define SERIAL_USART_CTRL1 (USART_CTRL1_PEN | USART_CTRL1_PSEL | USART_CTRL1_DBN0) // parity enable, odd parity, 9 bit length
# endif
# if !defined(SERIAL_USART_CTRL2)
# define SERIAL_USART_CTRL2 (USART_CTRL2_STOPBN_1) // 2 stop bits
# endif
# if !defined(SERIAL_USART_CTRL3)
# define SERIAL_USART_CTRL3 0
# endif
# if defined(USART1_REMAP)
# define USART_REMAP \
do { \
(IOMUX->REMAP |= IOMUX_REMAP_USART1_MUX); \
} while (0)
# elif defined(USART3_PARTIALREMAP)
# define USART_REMAP \
do { \
(IOMUX->REMAP |= IOMUX_REMAP_USART3_MUX_MUX1); \
} while (0)
# elif defined(USART3_FULLREMAP)
# define USART_REMAP \
do { \
(IOMUX->REMAP |= IOMUX_REMAP_USART3_MUX_MUX2); \
} while (0)
# endif
#endif

155
platforms/chibios/drivers/spi_master.c
View file

@ -19,13 +19,33 @@
#include "timer.h"
static bool spiStarted = false;
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
static pin_t currentSlavePin;
static pin_t current_slave_pin = NO_PIN;
static bool current_cs_active_low = true;
#endif
static SPIConfig spiConfig;
static inline void spi_select(void) {
spiSelect(&SPI_DRIVER);
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
if (current_slave_pin != NO_PIN) {
gpio_write_pin(current_slave_pin, current_cs_active_low ? 0 : 1);
}
#endif
}
static inline void spi_unselect(void) {
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
if (current_slave_pin != NO_PIN) {
gpio_write_pin(current_slave_pin, current_cs_active_low ? 1 : 0);
}
#endif
spiUnselect(&SPI_DRIVER);
}
__attribute__((weak)) void spi_init(void) {
static bool is_initialised = false;
if (!is_initialised) {
@ -63,7 +83,7 @@ __attribute__((weak)) void spi_init(void) {
}
}
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
bool spi_start_extended(spi_start_config_t *start_config) {
#if (SPI_USE_MUTUAL_EXCLUSION == TRUE)
spiAcquireBus(&SPI_DRIVER);
#endif // (SPI_USE_MUTUAL_EXCLUSION == TRUE)
@ -71,32 +91,37 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
if (spiStarted) {
return false;
}
#if SPI_SELECT_MODE != SPI_SELECT_MODE_NONE
if (slavePin == NO_PIN) {
if (start_config->slave_pin == NO_PIN) {
return false;
}
#endif
#if !(defined(WB32F3G71xx) || defined(WB32FQ95xx))
uint16_t roundedDivisor = 2;
while (roundedDivisor < divisor) {
while (roundedDivisor < start_config->divisor) {
roundedDivisor <<= 1;
}
# if defined(AT32F415)
if (roundedDivisor < 2 || roundedDivisor > 1024) {
return false;
}
# else
if (roundedDivisor < 2 || roundedDivisor > 256) {
return false;
}
# endif
#endif
#if defined(K20x) || defined(KL2x)
spiConfig.tar0 = SPIx_CTARn_FMSZ(7) | SPIx_CTARn_ASC(1);
if (lsbFirst) {
if (start_config->lsb_first) {
spiConfig.tar0 |= SPIx_CTARn_LSBFE;
}
switch (mode) {
switch (start_config->mode) {
case 0:
break;
case 1:
@ -141,11 +166,11 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.cr0 = SPI_CR0_SELOEN;
spiConfig.cr1 = SPI_CR1_MODE | 8; // 8 bits and in master mode
if (lsbFirst) {
if (start_config->lsb_first) {
spiConfig.cr1 |= SPI_CR1_FIRSTBIT;
}
switch (mode) {
switch (start_config->mode) {
case 0:
spiConfig.cr1 |= SPI_CR1_FORMAT_MODE0;
break;
@ -163,17 +188,17 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.cpr = (roundedDivisor - 1) >> 1;
#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
if (!lsbFirst) {
osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
if (!start_config->lsb_first) {
osalDbgAssert(start_config->lsb_first != FALSE, "unsupported lsb_first");
}
if (divisor < 1) {
if (start_config->divisor < 1) {
return false;
}
spiConfig.SPI_BaudRatePrescaler = (divisor << 2);
spiConfig.SPI_BaudRatePrescaler = (start_config->divisor << 2);
switch (mode) {
switch (start_config->mode) {
case 0:
spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
spiConfig.SPI_CPOL = SPI_CPOL_Low;
@ -192,8 +217,8 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
break;
}
#elif defined(MCU_RP)
if (lsbFirst) {
osalDbgAssert(lsbFirst == false, "RP2040s PrimeCell SPI implementation does not support sending LSB first.");
if (start_config->lsb_first) {
osalDbgAssert(start_config->lsb_first == false, "RP2040s PrimeCell SPI implementation does not support sending LSB first.");
}
// Motorola frame format and 8bit transfer data size.
@ -203,7 +228,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
// passed divisor to be the only value to divide the input clock by.
spiConfig.SSPCPSR = roundedDivisor; // Even number from 2 to 254
switch (mode) {
switch (start_config->mode) {
case 0:
spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPO; // Clock polarity: low
spiConfig.SSPCR0 &= ~SPI_SSPCR0_SPH; // Clock phase: sample on first edge
@ -221,14 +246,67 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiConfig.SSPCR0 |= SPI_SSPCR0_SPH; // Clock phase: sample on second edge transition
break;
}
#elif defined(AT32F415)
spiConfig.ctrl1 = 0;
if (start_config->lsb_first) {
spiConfig.ctrl1 |= SPI_CTRL1_LTF;
}
switch (start_config->mode) {
case 0:
break;
case 1:
spiConfig.ctrl1 |= SPI_CTRL1_CLKPHA;
break;
case 2:
spiConfig.ctrl1 |= SPI_CTRL1_CLKPOL;
break;
case 3:
spiConfig.ctrl1 |= SPI_CTRL1_CLKPHA | SPI_CTRL1_CLKPOL;
break;
}
switch (roundedDivisor) {
case 2:
break;
case 4:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_0;
break;
case 8:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_1;
break;
case 16:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0;
break;
case 32:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2;
break;
case 64:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_0;
break;
case 128:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1;
break;
case 256:
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0;
break;
case 512:
spiConfig.ctrl2 |= SPI_CTRL1_MDIV_3;
break;
case 1024:
spiConfig.ctrl2 |= SPI_CTRL1_MDIV_3;
spiConfig.ctrl1 |= SPI_CTRL1_MDIV_0;
break;
}
#else
spiConfig.cr1 = 0;
if (lsbFirst) {
if (start_config->lsb_first) {
spiConfig.cr1 |= SPI_CR1_LSBFIRST;
}
switch (mode) {
switch (start_config->mode) {
case 0:
break;
case 1:
@ -271,31 +349,37 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spiStarted = true;
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
currentSlavePin = slavePin;
current_slave_pin = start_config->slave_pin;
current_cs_active_low = start_config->cs_active_low;
#endif
#if SPI_SELECT_MODE == SPI_SELECT_MODE_PAD
spiConfig.ssport = PAL_PORT(slavePin);
spiConfig.sspad = PAL_PAD(slavePin);
gpio_set_pin_output(slavePin);
spiConfig.ssport = PAL_PORT(start_config->slave_pin);
spiConfig.sspad = PAL_PAD(start_config->slave_pin);
gpio_set_pin_output(start_config->slave_pin);
#elif SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
if (slavePin != NO_PIN) {
gpio_set_pin_output(slavePin);
if (start_config->slave_pin != NO_PIN) {
gpio_set_pin_output(start_config->slave_pin);
}
#else
# error "Unsupported SPI_SELECT_MODE"
#endif
spiStart(&SPI_DRIVER, &spiConfig);
spiSelect(&SPI_DRIVER);
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
if (slavePin != NO_PIN) {
gpio_write_pin_low(slavePin);
}
#endif
spi_select();
return true;
}
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
spi_start_config_t start_config = {0};
start_config.slave_pin = slavePin;
start_config.lsb_first = lsbFirst;
start_config.mode = mode;
start_config.divisor = divisor;
start_config.cs_active_low = true;
return spi_start_extended(&start_config);
}
spi_status_t spi_write(uint8_t data) {
uint8_t rxData;
spiExchange(&SPI_DRIVER, 1, &data, &rxData);
@ -322,12 +406,7 @@ spi_status_t spi_receive(uint8_t *data, uint16_t length) {
void spi_stop(void) {
if (spiStarted) {
#if SPI_SELECT_MODE == SPI_SELECT_MODE_NONE
if (currentSlavePin != NO_PIN) {
gpio_write_pin_high(currentSlavePin);
}
#endif
spiUnselect(&SPI_DRIVER);
spi_unselect();
spiStop(&SPI_DRIVER);
spiStarted = false;
}

9
platforms/chibios/drivers/spi_master.h
View file

@ -75,9 +75,18 @@ typedef int16_t spi_status_t;
#ifdef __cplusplus
extern "C" {
#endif
typedef struct spi_start_config_t {
pin_t slave_pin;
bool lsb_first;
uint8_t mode;
uint16_t divisor;
bool cs_active_low;
} spi_start_config_t;
void spi_init(void);
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
bool spi_start_extended(spi_start_config_t *start_config);
spi_status_t spi_write(uint8_t data);

27
platforms/chibios/drivers/vendor/RP/RP2040/ws2812_vendor.c vendored
View file

@ -266,19 +266,36 @@ static inline void sync_ws2812_transfer(void) {
busy_wait_until(LAST_TRANSFER);
}
void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
#if defined(WS2812_RGBW)
ws2812_rgb_to_rgbw(&ws2812_leds[index]);
#endif
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
sync_ws2812_transfer();
for (int i = 0; i < leds; i++) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
#if defined(WS2812_RGBW)
WS2812_BUFFER[i] = rgbw8888_to_u32(ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
WS2812_BUFFER[i] = rgbw8888_to_u32(ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, ws2812_leds[i].w);
#else
WS2812_BUFFER[i] = rgbw8888_to_u32(ledarray[i].r, ledarray[i].g, ledarray[i].b, 0);
WS2812_BUFFER[i] = rgbw8888_to_u32(ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, 0);
#endif
}
dmaChannelSetSourceX(dma_channel, (uint32_t)WS2812_BUFFER);
dmaChannelSetCounterX(dma_channel, leds);
dmaChannelSetCounterX(dma_channel, WS2812_LED_COUNT);
dmaChannelSetModeX(dma_channel, RP_DMA_MODE_WS2812);
dmaChannelEnableX(dma_channel);
}

2
platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c
View file

@ -33,7 +33,7 @@ static inline uint32_t detect_flash_size(void) {
#elif defined(FLASH_SIZE)
return FLASH_SIZE;
#elif defined(FLASHSIZE_BASE)
# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_SERIES_GD32VF103)
# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_SERIES_AT32F415) || defined(QMK_MCU_SERIES_GD32VF103)
return ((*(uint32_t *)FLASHSIZE_BASE) & 0xFFFFU) << 10U; // this register has the flash size in kB, so we convert it to bytes
# elif defined(QMK_MCU_SERIES_STM32L1XX)
# error This MCU family has an uncommon flash size register definition and has not been implemented. Perhaps try using the true EEPROM on the MCU instead?

2
platforms/chibios/drivers/wear_leveling/wear_leveling_efl_config.h
View file

@ -16,6 +16,8 @@
# define BACKING_STORE_WRITE_SIZE 4 // from hal_efl_lld.c
# elif defined(QMK_MCU_FAMILY_WB32)
# define BACKING_STORE_WRITE_SIZE 8 // from hal_efl_lld.c
# elif defined(QMK_MCU_FAMILY_AT32)
# define BACKING_STORE_WRITE_SIZE 2 // from hal_efl_lld.c
# elif defined(QMK_MCU_FAMILY_STM32)
# if defined(STM32_FLASH_LINE_SIZE) // from some family's stm32_registry.h file
# define BACKING_STORE_WRITE_SIZE (STM32_FLASH_LINE_SIZE)

44
platforms/chibios/drivers/ws2812_bitbang.c
View file

@ -11,7 +11,7 @@
/* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */
#ifndef WS2812_BITBANG_NOP_FUDGE
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415)
# define WS2812_BITBANG_NOP_FUDGE 0.4
# else
# if defined(RP2040)
@ -76,33 +76,49 @@ void sendByte(uint8_t byte) {
}
}
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_init(void) {
palSetLineMode(WS2812_DI_PIN, WS2812_OUTPUT_MODE);
}
// Setleds for standard RGB
void ws2812_setleds(rgb_led_t *ledarray, uint16_t leds) {
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
#if defined(WS2812_RGBW)
ws2812_rgb_to_rgbw(&ws2812_leds[index]);
#endif
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
// this code is very time dependent, so we need to disable interrupts
chSysLock();
for (uint8_t i = 0; i < leds; i++) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
// WS2812 protocol dictates grb order
#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
sendByte(ledarray[i].g);
sendByte(ledarray[i].r);
sendByte(ledarray[i].b);
sendByte(ws2812_leds[i].g);
sendByte(ws2812_leds[i].r);
sendByte(ws2812_leds[i].b);
#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_RGB)
sendByte(ledarray[i].r);
sendByte(ledarray[i].g);
sendByte(ledarray[i].b);
sendByte(ws2812_leds[i].r);
sendByte(ws2812_leds[i].g);
sendByte(ws2812_leds[i].b);
#elif (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_BGR)
sendByte(ledarray[i].b);
sendByte(ledarray[i].g);
sendByte(ledarray[i].r);
sendByte(ws2812_leds[i].b);
sendByte(ws2812_leds[i].g);
sendByte(ws2812_leds[i].r);
#endif
#ifdef WS2812_RGBW
sendByte(ledarray[i].w);
sendByte(ws2812_leds[i].w);
#endif
}

91
platforms/chibios/drivers/ws2812_pwm.c
View file

@ -40,6 +40,9 @@
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_ID)
# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_ID STM32_DMAMUX1_TIM?_UP"
#endif
#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_CHANNEL) && !defined(WS2812_PWM_DMAMUX_ID)
# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_CHANNEL 1, #define WS2812_PWM_DMAMUX_ID AT32_DMAMUX_TMR?_OVERFLOW"
#endif
/* Summarize https://www.st.com/resource/en/application_note/an4013-stm32-crossseries-timer-overview-stmicroelectronics.pdf to
* figure out if we are using a 32bit timer. This is needed to setup the DMA controller correctly.
@ -79,15 +82,15 @@
# endif
#endif
#ifndef WS2812_PWM_TARGET_PERIOD
//# define WS2812_PWM_TARGET_PERIOD 800000 // Original code is 800k...?
# define WS2812_PWM_TARGET_PERIOD 80000 // TODO: work out why 10x less on f303/f4x1
// Default is 800000Hz, which has a period of 1.25us
#ifndef WS2812_PWM_FREQUENCY
# define WS2812_PWM_FREQUENCY (1000000000 / WS2812_TIMING)
#endif
/* --- PRIVATE CONSTANTS ---------------------------------------------------- */
#define WS2812_PWM_FREQUENCY (CPU_CLOCK / 2) /**< Clock frequency of PWM, must be valid with respect to system clock! */
#define WS2812_PWM_PERIOD (WS2812_PWM_FREQUENCY / WS2812_PWM_TARGET_PERIOD) /**< Clock period in ticks. 1 / 800kHz = 1.25 uS (as per datasheet) */
#define WS2812_PWM_TICK_FREQUENCY (CPU_CLOCK / 2) /**< Clock frequency of PWM ticks, must be valid with respect to system clock! */
#define WS2812_PWM_PERIOD (WS2812_PWM_TICK_FREQUENCY / WS2812_PWM_FREQUENCY) /**< Clock period in PWM ticks. */
/**
* @brief Number of bit-periods to hold the data line low at the end of a frame
@ -102,37 +105,16 @@
/**
* @brief High period for a zero, in ticks
*
* Per the datasheet:
* WS2812:
* - T0H: 200 nS to 500 nS, inclusive
* - T0L: 650 nS to 950 nS, inclusive
* WS2812B:
* - T0H: 200 nS to 500 nS, inclusive
* - T0L: 750 nS to 1050 nS, inclusive
*
* The duty cycle is calculated for a high period of 350 nS.
*/
#define WS2812_DUTYCYCLE_0 (WS2812_PWM_FREQUENCY / (1000000000 / 350))
#define WS2812_DUTYCYCLE_0 (WS2812_PWM_TICK_FREQUENCY / (1000000000 / WS2812_T0H))
#if (WS2812_DUTYCYCLE_0 > 255)
# error WS2812 PWM driver: High period for a 0 is more than a byte
#endif
/**
* @brief High period for a one, in ticks
*
* Per the datasheet:
* WS2812:
* - T1H: 550 nS to 850 nS, inclusive
* - T1L: 450 nS to 750 nS, inclusive
* WS2812B:
* - T1H: 750 nS to 1050 nS, inclusive
* - T1L: 200 nS to 500 nS, inclusive
*
* The duty cycle is calculated for a high period of 800 nS.
* This is in the middle of the specifications of the WS2812 and WS2812B.
*/
#define WS2812_DUTYCYCLE_1 (WS2812_PWM_FREQUENCY / (1000000000 / 800))
#define WS2812_DUTYCYCLE_1 (WS2812_PWM_TICK_FREQUENCY / (1000000000 / WS2812_T1H))
#if (WS2812_DUTYCYCLE_1 > 255)
# error WS2812 PWM driver: High period for a 1 is more than a byte
#endif
@ -290,6 +272,14 @@ typedef uint32_t ws2812_buffer_t;
# define WS2812_PWM_DMA_PERIPHERAL_WIDTH STM32_DMA_CR_PSIZE_HWORD
typedef uint16_t ws2812_buffer_t;
# endif
#elif defined(AT32F415)
# define WS2812_PWM_DMA_MEMORY_WIDTH AT32_DMA_CCTRL_MWIDTH_BYTE
# if defined(WS2812_PWM_TIMER_32BIT)
# define WS2812_PWM_DMA_PERIPHERAL_WIDTH AT32_DMA_CCTRL_PWIDTH_WORD
# else
# define WS2812_PWM_DMA_PERIPHERAL_WIDTH AT32_DMA_CCTRL_PWIDTH_HWORD
# endif
typedef uint8_t ws2812_buffer_t;
#else
# define WS2812_PWM_DMA_MEMORY_WIDTH STM32_DMA_CR_MSIZE_BYTE
# if defined(WS2812_PWM_TIMER_32BIT)
@ -322,7 +312,7 @@ void ws2812_init(void) {
// PWM Configuration
//#pragma GCC diagnostic ignored "-Woverride-init" // Turn off override-init warning for this struct. We use the overriding ability to set a "default" channel config
static const PWMConfig ws2812_pwm_config = {
.frequency = WS2812_PWM_FREQUENCY,
.frequency = WS2812_PWM_TICK_FREQUENCY,
.period = WS2812_PWM_PERIOD, // Mit dieser Periode wird UDE-Event erzeugt und ein neuer Wert (Länge WS2812_BIT_N) vom DMA ins CCR geschrieben
.callback = NULL,
.channels =
@ -330,8 +320,13 @@ void ws2812_init(void) {
[0 ... 3] = {.mode = PWM_OUTPUT_DISABLED, .callback = NULL}, // Channels default to disabled
[WS2812_PWM_CHANNEL - 1] = {.mode = WS2812_PWM_OUTPUT_MODE, .callback = NULL}, // Turn on the channel we care about
},
#if defined(AT32F415)
.ctrl2 = 0,
.iden = AT32_TMR_IDEN_OVFDEN, // DMA on update event for next period
#else
.cr2 = 0,
.dier = TIM_DIER_UDE, // DMA on update event for next period
#endif
};
//#pragma GCC diagnostic pop // Restore command-line warning options
@ -342,6 +337,11 @@ void ws2812_init(void) {
dmaStreamSetSource(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer);
dmaStreamSetDestination(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
dmaStreamSetMode(WS2812_PWM_DMA_STREAM, WB32_DMA_CHCFG_HWHIF(WS2812_PWM_DMA_CHANNEL) | WB32_DMA_CHCFG_DIR_M2P | WB32_DMA_CHCFG_PSIZE_WORD | WB32_DMA_CHCFG_MSIZE_WORD | WB32_DMA_CHCFG_MINC | WB32_DMA_CHCFG_CIRC | WB32_DMA_CHCFG_TCIE | WB32_DMA_CHCFG_PL(3));
#elif defined(AT32F415)
dmaStreamAlloc(WS2812_PWM_DMA_STREAM - AT32_DMA_STREAM(0), 10, NULL, NULL);
dmaStreamSetPeripheral(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tmr->CDT[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
dmaStreamSetMemory0(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer);
dmaStreamSetMode(WS2812_PWM_DMA_STREAM, AT32_DMA_CCTRL_DTD_M2P | WS2812_PWM_DMA_PERIPHERAL_WIDTH | WS2812_PWM_DMA_MEMORY_WIDTH | AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_CHPL(3));
#else
dmaStreamAlloc(WS2812_PWM_DMA_STREAM - STM32_DMA_STREAM(0), 10, NULL, NULL);
dmaStreamSetPeripheral(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
@ -356,6 +356,11 @@ void ws2812_init(void) {
dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_ID);
#endif
#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE)
// If the MCU has a DMAMUX we need to assign the correct resource
dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_CHANNEL, WS2812_PWM_DMAMUX_ID);
#endif
// Start DMA
dmaStreamEnable(WS2812_PWM_DMA_STREAM);
@ -387,13 +392,29 @@ void ws2812_write_led_rgbw(uint16_t led_number, uint8_t r, uint8_t g, uint8_t b,
}
}
// Setleds for standard RGB
void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
for (uint16_t i = 0; i < leds; i++) {
#ifdef WS2812_RGBW
ws2812_write_led_rgbw(i, ledarray[i].r, ledarray[i].g, ledarray[i].b, ledarray[i].w);
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
#if defined(WS2812_RGBW)
ws2812_rgb_to_rgbw(&ws2812_leds[index]);
#endif
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
#if defined(WS2812_RGBW)
ws2812_write_led_rgbw(i, ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b, ws2812_leds[i].w);
#else
ws2812_write_led(i, ledarray[i].r, ledarray[i].g, ledarray[i].b);
ws2812_write_led(i, ws2812_leds[i].r, ws2812_leds[i].g, ws2812_leds[i].b);
#endif
}
}

96
platforms/chibios/drivers/ws2812_spi.c
View file

@ -40,26 +40,53 @@
// Define SPI config speed
// baudrate should target 3.2MHz
#if defined(AT32F415)
# if WS2812_SPI_DIVISOR == 2
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (0)
# elif WS2812_SPI_DIVISOR == 4
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_0)
# elif WS2812_SPI_DIVISOR == 8
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_1)
# elif WS2812_SPI_DIVISOR == 16 // default
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0)
# elif WS2812_SPI_DIVISOR == 32
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2)
# elif WS2812_SPI_DIVISOR == 64
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_0)
# elif WS2812_SPI_DIVISOR == 128
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1)
# elif WS2812_SPI_DIVISOR == 256
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_2 | SPI_CTRL1_MDIV_1 | SPI_CTRL1_MDIV_0)
# elif WS2812_SPI_DIVISOR == 512
# define WS2812_SPI_DIVISOR_CTRL2_MDIV_X (SPI_CTRL1_MDIV_3)
# elif WS2812_SPI_DIVISOR == 1024
# define WS2812_SPI_DIVISOR_CTRL2_MDIV_X (SPI_CTRL1_MDIV_3)
# define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_0)
# else
# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
# endif
#else
// F072 fpclk = 48MHz
// 48/16 = 3Mhz
#if WS2812_SPI_DIVISOR == 2
# define WS2812_SPI_DIVISOR_CR1_BR_X (0)
#elif WS2812_SPI_DIVISOR == 4
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_0)
#elif WS2812_SPI_DIVISOR == 8
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1)
#elif WS2812_SPI_DIVISOR == 16 // default
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#elif WS2812_SPI_DIVISOR == 32
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2)
#elif WS2812_SPI_DIVISOR == 64
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#elif WS2812_SPI_DIVISOR == 128
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#elif WS2812_SPI_DIVISOR == 256
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#else
# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
# if WS2812_SPI_DIVISOR == 2
# define WS2812_SPI_DIVISOR_CR1_BR_X (0)
# elif WS2812_SPI_DIVISOR == 4
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_0)
# elif WS2812_SPI_DIVISOR == 8
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1)
# elif WS2812_SPI_DIVISOR == 16 // default
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_1 | SPI_CR1_BR_0)
# elif WS2812_SPI_DIVISOR == 32
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2)
# elif WS2812_SPI_DIVISOR == 64
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_0)
# elif WS2812_SPI_DIVISOR == 128
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1)
# elif WS2812_SPI_DIVISOR == 256
# define WS2812_SPI_DIVISOR_CR1_BR_X (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
# else
# error "Configured WS2812_SPI_DIVISOR value is not supported at this time."
# endif
#endif
// Use SPI circular buffer
@ -106,7 +133,7 @@ static uint8_t get_protocol_eq(uint8_t data, int pos) {
return eq;
}
static void set_led_color_rgb(rgb_led_t color, int pos) {
static void set_led_color_rgb(ws2812_led_t color, int pos) {
uint8_t* tx_start = &txbuf[PREAMBLE_SIZE];
#if (WS2812_BYTE_ORDER == WS2812_BYTE_ORDER_GRB)
@ -137,6 +164,8 @@ static void set_led_color_rgb(rgb_led_t color, int pos) {
#endif
}
ws2812_led_t ws2812_leds[WS2812_LED_COUNT];
void ws2812_init(void) {
palSetLineMode(WS2812_DI_PIN, WS2812_MOSI_OUTPUT_MODE);
@ -174,8 +203,16 @@ void ws2812_init(void) {
NULL, // error_cb
PAL_PORT(WS2812_DI_PIN),
PAL_PAD(WS2812_DI_PIN),
# if defined(AT32F415)
WS2812_SPI_DIVISOR_CTRL1_MDIV_X,
# if (WS2812_SPI_DIVISOR == 512 || WS2812_SPI_DIVISOR == 1024)
WS2812_SPI_DIVISOR_CTRL2_MDIV_X,
# endif
0
# else
WS2812_SPI_DIVISOR_CR1_BR_X,
0
# endif
#endif
};
@ -187,9 +224,24 @@ void ws2812_init(void) {
#endif
}
void ws2812_setleds(rgb_led_t* ledarray, uint16_t leds) {
for (uint8_t i = 0; i < leds; i++) {
set_led_color_rgb(ledarray[i], i);
void ws2812_set_color(int index, uint8_t red, uint8_t green, uint8_t blue) {
ws2812_leds[index].r = red;
ws2812_leds[index].g = green;
ws2812_leds[index].b = blue;
#if defined(WS2812_RGBW)
ws2812_rgb_to_rgbw(&ws2812_leds[index]);
#endif
}
void ws2812_set_color_all(uint8_t red, uint8_t green, uint8_t blue) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
ws2812_set_color(i, red, green, blue);
}
}
void ws2812_flush(void) {
for (int i = 0; i < WS2812_LED_COUNT; i++) {
set_led_color_rgb(ws2812_leds[i], i);
}
// Send async - each led takes ~0.03ms, 50 leds ~1.5ms, animations flushing faster than send will cause issues.

2
platforms/chibios/flash.mk
View file

@ -113,6 +113,8 @@ else ifeq ($(strip $(MCU_FAMILY)),STM32)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else ifeq ($(strip $(MCU_FAMILY)),WB32)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_WB32_DFU_UPDATER)
else ifeq ($(strip $(MCU_FAMILY)),AT32)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else ifeq ($(strip $(MCU_FAMILY)),GD32V)
$(UNSYNC_OUTPUT_CMD) && $(call EXEC_DFU_UTIL)
else

34
platforms/chibios/mcu_selection.mk
View file

@ -809,6 +809,40 @@ ifneq ($(findstring WB32FQ95, $(MCU)),)
WB32_BOOTLOADER_ADDRESS ?= 0x1FFFE000
endif
ifneq ($(findstring AT32F415, $(MCU)),)
# Cortex version
MCU = cortex-m4
# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
ARMV = 7
## chip/board settings
# - the next two should match the directories in
# <chibios[-contrib]>/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)
# OR
# <chibios[-contrib]>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
MCU_FAMILY = AT32
MCU_SERIES = AT32F415
# Linker script to use
# - it should exist either in <chibios>/os/common/startup/ARMCMx/compilers/GCC/ld/
# or <keyboard_dir>/ld/
MCU_LDSCRIPT ?= AT32F415xB
# Startup code to use
# - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
MCU_STARTUP ?= at32f415
# Board: it should exist either in <chibios>/os/hal/boards/,
# <keyboard_dir>/boards/, or drivers/boards/
BOARD ?= GENERIC_AT32_F415XX
USE_FPU ?= no
# Bootloader address for AT32 DFU
AT32_BOOTLOADER_ADDRESS ?= 0x1FFFAC00
endif
ifneq ($(findstring GD32VF103, $(MCU)),)
# RISC-V
MCU = risc-v

4
platforms/chibios/platform.mk
View file

@ -155,6 +155,10 @@ ifdef WB32_BOOTLOADER_ADDRESS
OPT_DEFS += -DWB32_BOOTLOADER_ADDRESS=$(WB32_BOOTLOADER_ADDRESS)
endif
ifdef AT32_BOOTLOADER_ADDRESS
OPT_DEFS += -DAT32_BOOTLOADER_ADDRESS=$(AT32_BOOTLOADER_ADDRESS)
endif
# Work out if we need to set up the include for the bootloader definitions
ifneq ("$(wildcard $(KEYBOARD_PATH_5)/bootloader_defs.h)","")
OPT_DEFS += -include $(KEYBOARD_PATH_5)/bootloader_defs.h

21
platforms/chibios/timer.c
View file

@ -5,6 +5,7 @@
static uint32_t ticks_offset = 0;
static uint32_t last_ticks = 0;
static uint32_t ms_offset = 0;
static uint32_t saved_ms = 0;
#if CH_CFG_ST_RESOLUTION < 32
static uint32_t last_systime = 0;
static uint32_t overflow = 0;
@ -73,6 +74,26 @@ void timer_clear(void) {
chSysUnlock();
}
__attribute__((weak)) void platform_timer_save_value(uint32_t value) {
saved_ms = value;
}
__attribute__((weak)) uint32_t platform_timer_restore_value(void) {
return saved_ms;
}
void timer_restore(void) {
chSysLock();
ticks_offset = get_system_time_ticks();
last_ticks = 0;
ms_offset = platform_timer_restore_value();
chSysUnlock();
}
void timer_save(void) {
platform_timer_save_value(timer_read32());
}
uint16_t timer_read(void) {
return (uint16_t)timer_read32();
}

2
platforms/timer.h
View file

@ -38,6 +38,8 @@ extern volatile uint32_t timer_count;
void timer_init(void);
void timer_clear(void);
void timer_save(void);
void timer_restore(void);
uint16_t timer_read(void);
uint32_t timer_read32(void);
uint16_t timer_elapsed(uint16_t last);