Added MCU support for ArteryTek AT32F415 (#23445)
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HorrorTroll
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parent
074bbbfb21
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32 changed files with 1065 additions and 63 deletions
101
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
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101
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.c
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@ -0,0 +1,101 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2023..2024 HorrorTroll
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ChibiOS - Copyright (C) 2023..2024 Zhaqian
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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const PALConfig pal_default_config =
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{
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{VAL_GPIOAODT, VAL_GPIOACFGLR, VAL_GPIOACFGHR},
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{VAL_GPIOBODT, VAL_GPIOBCFGLR, VAL_GPIOBCFGHR},
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#if AT32_HAS_GPIOC
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{VAL_GPIOCODT, VAL_GPIOCCFGLR, VAL_GPIOCCFGHR},
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#endif
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{VAL_GPIODODT, VAL_GPIODCFGLR, VAL_GPIODCFGHR},
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#if AT32_HAS_GPIOF
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{VAL_GPIOFODT, VAL_GPIOFCFGLR, VAL_GPIOFCFGHR},
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#endif
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};
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Early initialization code.
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* @details System clocks are initialized before everything else.
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*/
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void __early_init(void) {
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at32_clock_init();
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}
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#if HAL_USE_SDC || defined(__DOXYGEN__)
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/**
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* @brief SDC card detection.
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*/
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bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
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static bool last_status = false;
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if (blkIsTransferring(sdcp))
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return last_status;
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return last_status = (bool)palReadPad(GPIOC, GPIOC_PIN11);
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}
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/**
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* @brief SDC card write protection detection.
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*/
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bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
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(void)sdcp;
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return false;
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}
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#endif /* HAL_USE_SDC */
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/**
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* @brief Board-specific initialization code.
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* @note You can add your board-specific code here.
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*/
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void boardInit(void) {
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IOMUX->REMAP |= IOMUX_REMAP_SWJTAG_MUX_JTAGDIS;
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}
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207
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
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207
platforms/chibios/boards/GENERIC_AT32_F415XX/board/board.h
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@ -0,0 +1,207 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2023..2024 HorrorTroll
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ChibiOS - Copyright (C) 2023..2024 Zhaqian
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*
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* Setup for a Generic AT32F415 board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_GENERIC_AT32_F415XX
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#define BOARD_NAME "GENERIC AT32F415 board"
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/*
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* Board oscillators-related settings.
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*/
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#if !defined(AT32_LEXTCLK)
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#define AT32_LEXTCLK 32768
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#endif
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#if !defined(AT32_HEXTCLK)
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#define AT32_HEXTCLK 8000000
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#endif
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/*
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* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
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*/
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#define AT32F415KB
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/*
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* IO pins assignments.
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*/
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#define GPIOA_PIN0 0U
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#define GPIOA_PIN1 1U
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#define GPIOA_PIN2 2U
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#define GPIOA_PIN3 3U
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#define GPIOA_PIN4 4U
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#define GPIOA_PIN5 5U
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#define GPIOA_PIN6 6U
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#define GPIOA_PIN7 7U
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#define GPIOA_PIN8 8U
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#define GPIOA_PIN9 9U
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#define GPIOA_PIN10 10U
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#define GPIOA_PIN11 11U
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#define GPIOA_PIN12 12U
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#define GPIOA_SWDIO 13U
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#define GPIOA_SWCLK 14U
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#define GPIOA_PIN15 15U
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#define GPIOB_PIN0 0U
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#define GPIOB_PIN1 1U
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#define GPIOB_PIN2 2U
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#define GPIOB_PIN3 3U
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#define GPIOB_PIN4 4U
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#define GPIOB_PIN5 5U
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#define GPIOB_PIN6 6U
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#define GPIOB_PIN7 7U
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#define GPIOB_PIN8 8U
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#define GPIOB_PIN9 9U
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#define GPIOB_PIN10 10U
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#define GPIOB_PIN11 11U
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#define GPIOB_PIN12 12U
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#define GPIOB_PIN13 13U
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#define GPIOB_PIN14 14U
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#define GPIOB_PIN15 15U
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#define GPIOC_PIN0 0U
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#define GPIOC_PIN1 1U
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#define GPIOC_PIN2 2U
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#define GPIOC_PIN3 3U
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#define GPIOC_PIN4 4U
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#define GPIOC_PIN5 5U
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#define GPIOC_PIN6 6U
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#define GPIOC_PIN7 7U
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#define GPIOC_PIN8 8U
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#define GPIOC_PIN9 9U
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#define GPIOC_PIN10 10U
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#define GPIOC_PIN11 11U
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#define GPIOC_PIN12 12U
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#define GPIOC_PIN13 13U
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#define GPIOC_PIN14 14U
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#define GPIOC_PIN15 15U
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#define GPIOD_HEXT_IN 0U
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#define GPIOD_HEXT_OUT 1U
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#define GPIOD_PIN2 2U
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#define GPIOF_PIN4 4U
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#define GPIOF_PIN5 5U
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#define GPIOF_PIN6 6U
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#define GPIOF_PIN7 7U
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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*
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* The digits have the following meaning:
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* 0 - Analog input.
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* 1 - Push Pull output 10MHz.
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* 2 - Push Pull output 2MHz.
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* 3 - Push Pull output 50MHz.
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* 4 - Digital input.
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* 5 - Open Drain output 10MHz.
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* 6 - Open Drain output 2MHz.
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* 7 - Open Drain output 50MHz.
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* 8 - Digital input with Pull-Up or Pull-Down resistor depending on ODT.
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* 9 - Alternate Push Pull output 10MHz.
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* A - Alternate Push Pull output 2MHz.
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* B - Alternate Push Pull output 50MHz.
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* C - Reserved.
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* D - Alternate Open Drain output 10MHz.
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* E - Alternate Open Drain output 2MHz.
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* F - Alternate Open Drain output 50MHz.
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* Please refer to the AT32 Reference Manual for details.
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*/
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/*
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* Port A setup.
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*/
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#define VAL_GPIOACFGLR 0x88888B88 /* PA7...PA0 */
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#define VAL_GPIOACFGHR 0x888888B8 /* PA15...PA8 */
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#define VAL_GPIOAODT 0xFFFFFFFF
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/*
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* Port B setup.
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*/
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#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */
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#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */
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#define VAL_GPIOBODT 0xFFFFFFFF
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/*
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* Port C setup.
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*/
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#define VAL_GPIOCCFGLR 0x88888888 /* PC7...PC0 */
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#define VAL_GPIOCCFGHR 0x88888888 /* PC15...PC8 */
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#define VAL_GPIOCODT 0xFFFFFFFF
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/*
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* Port D setup.
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* Everything input with pull-up except:
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* PD0 - Normal input (GPIOD_HEXT_IN).
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* PD1 - Normal input (GPIOD_HEXT_OUT).
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*/
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#define VAL_GPIODCFGLR 0x88888844 /* PD7...PD0 */
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#define VAL_GPIODCFGHR 0x88888888 /* PD15...PD8 */
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#define VAL_GPIODODT 0xFFFFFFFF
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/*
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* Port F setup.
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*/
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#define VAL_GPIOFCFGLR 0x88888888 /* PF7...PF0 */
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#define VAL_GPIOFCFGHR 0x88888888 /* PF15...PF8 */
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#define VAL_GPIOFODT 0xFFFFFFFF
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FROM_ASM_ */
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#endif /* _BOARD_H_ */
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# List of all the board related files.
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BOARDSRC = $(BOARD_PATH)/board/board.c
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# Required include directories
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BOARDINC = $(BOARD_PATH)/board
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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// Copyright 2023-2024 HorrorTroll <https://github.com/HorrorTroll>
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// Copyright 2023-2024 Zhaqian <https://github.com/zhaqian12>
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#define BOARD_OTG_VBUSIG
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#define USB_ENDPOINTS_ARE_REORDERABLE
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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236
platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
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236
platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2023..2024 HorrorTroll
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ChibiOS - Copyright (C) 2023..2024 Zhaqian
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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|
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
|
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* AT32F415 drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define AT32F415_MCUCONF
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/*
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* General settings.
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*/
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#define AT32_NO_INIT FALSE
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/*
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* HAL driver system settings.
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*/
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#define AT32_HICK_ENABLED TRUE
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#define AT32_LICK_ENABLED FALSE
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#define AT32_HEXT_ENABLED TRUE
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#define AT32_LEXT_ENABLED FALSE
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#define AT32_SCLKSEL AT32_SCLKSEL_PLL
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#define AT32_PLLRCS AT32_PLLRCS_HEXT
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#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1
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#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID
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#define AT32_PLLMULT_VALUE 18
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#define AT32_PLL_FR_VALUE 4
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#define AT32_PLL_MS_VALUE 1
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#define AT32_PLL_NS_VALUE 72
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#define AT32_AHBDIV AT32_AHBDIV_DIV1
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#define AT32_APB1DIV AT32_APB1DIV_DIV2
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#define AT32_APB2DIV AT32_APB2DIV_DIV2
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#define AT32_ADCDIV AT32_ADCDIV_DIV4
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#define AT32_USB_CLOCK_REQUIRED TRUE
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#define AT32_USBDIV AT32_USBDIV_DIV3
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#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK
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#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1
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#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV
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#define AT32_PVM_ENABLE FALSE
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#define AT32_PVMSEL AT32_PVMSEL_LEV1
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/*
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* IRQ system settings.
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*/
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#define AT32_IRQ_EXINT0_PRIORITY 6
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#define AT32_IRQ_EXINT1_PRIORITY 6
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#define AT32_IRQ_EXINT2_PRIORITY 6
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#define AT32_IRQ_EXINT3_PRIORITY 6
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#define AT32_IRQ_EXINT4_PRIORITY 6
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#define AT32_IRQ_EXINT5_9_PRIORITY 6
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#define AT32_IRQ_EXINT10_15_PRIORITY 6
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#define AT32_IRQ_EXINT16_PRIORITY 6
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#define AT32_IRQ_EXINT17_PRIORITY 15
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#define AT32_IRQ_EXINT18_PRIORITY 6
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#define AT32_IRQ_EXINT19_PRIORITY 6
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#define AT32_IRQ_EXINT20_PRIORITY 6
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#define AT32_IRQ_EXINT21_PRIORITY 15
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#define AT32_IRQ_EXINT22_PRIORITY 15
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#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7
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#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7
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#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7
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#define AT32_IRQ_TMR1_CH_PRIORITY 7
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#define AT32_IRQ_TMR2_PRIORITY 7
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#define AT32_IRQ_TMR3_PRIORITY 7
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#define AT32_IRQ_TMR4_PRIORITY 7
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#define AT32_IRQ_TMR5_PRIORITY 7
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#define AT32_IRQ_USART1_PRIORITY 12
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#define AT32_IRQ_USART2_PRIORITY 12
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#define AT32_IRQ_USART3_PRIORITY 12
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#define AT32_IRQ_UART4_PRIORITY 12
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#define AT32_IRQ_UART5_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define AT32_ADC_USE_ADC1 FALSE
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#define AT32_ADC_ADC1_DMA_PRIORITY 2
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#define AT32_ADC_ADC1_IRQ_PRIORITY 6
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/*
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* CAN driver system settings.
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*/
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#define AT32_CAN_USE_CAN1 FALSE
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#define AT32_CAN_CAN1_IRQ_PRIORITY 11
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/*
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* DMA driver system settings.
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*/
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#define AT32_DMA_USE_DMAMUX TRUE
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/*
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* GPT driver system settings.
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*/
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#define AT32_GPT_USE_TMR1 FALSE
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#define AT32_GPT_USE_TMR2 FALSE
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#define AT32_GPT_USE_TMR3 FALSE
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#define AT32_GPT_USE_TMR4 FALSE
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#define AT32_GPT_USE_TMR5 FALSE
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#define AT32_GPT_USE_TMR9 FALSE
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#define AT32_GPT_USE_TMR10 FALSE
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#define AT32_GPT_USE_TMR11 FALSE
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/*
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* I2C driver system settings.
|
||||
*/
|
||||
#define AT32_I2C_USE_I2C1 FALSE
|
||||
#define AT32_I2C_USE_I2C2 FALSE
|
||||
#define AT32_I2C_BUSY_TIMEOUT 50
|
||||
#define AT32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define AT32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define AT32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define AT32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define AT32_ICU_USE_TMR1 FALSE
|
||||
#define AT32_ICU_USE_TMR2 FALSE
|
||||
#define AT32_ICU_USE_TMR3 FALSE
|
||||
#define AT32_ICU_USE_TMR4 FALSE
|
||||
#define AT32_ICU_USE_TMR5 FALSE
|
||||
#define AT32_ICU_USE_TMR9 FALSE
|
||||
#define AT32_ICU_USE_TMR10 FALSE
|
||||
#define AT32_ICU_USE_TMR11 FALSE
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define AT32_PWM_USE_TMR1 FALSE
|
||||
#define AT32_PWM_USE_TMR2 FALSE
|
||||
#define AT32_PWM_USE_TMR3 FALSE
|
||||
#define AT32_PWM_USE_TMR4 FALSE
|
||||
#define AT32_PWM_USE_TMR5 FALSE
|
||||
#define AT32_PWM_USE_TMR9 FALSE
|
||||
#define AT32_PWM_USE_TMR10 FALSE
|
||||
#define AT32_PWM_USE_TMR11 FALSE
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define AT32_ERTC_DIVA_VALUE 32
|
||||
#define AT32_ERTC_DIVB_VALUE 1024
|
||||
#define AT32_ERTC_CTRL_INIT 0
|
||||
#define AT32_ERTC_TAMP_INIT 0
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define AT32_SDC_SDIO_DMA_PRIORITY 3
|
||||
#define AT32_SDC_SDIO_IRQ_PRIORITY 9
|
||||
#define AT32_SDC_WRITE_TIMEOUT_MS 1000
|
||||
#define AT32_SDC_READ_TIMEOUT_MS 1000
|
||||
#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10
|
||||
#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define AT32_SERIAL_USE_USART1 FALSE
|
||||
#define AT32_SERIAL_USE_USART2 FALSE
|
||||
#define AT32_SERIAL_USE_USART3 FALSE
|
||||
#define AT32_SERIAL_USE_UART4 FALSE
|
||||
#define AT32_SERIAL_USE_UART5 FALSE
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define AT32_SPI_USE_SPI1 FALSE
|
||||
#define AT32_SPI_USE_SPI2 FALSE
|
||||
#define AT32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define AT32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define AT32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define AT32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define AT32_ST_IRQ_PRIORITY 8
|
||||
#define AT32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define AT32_UART_USE_USART1 FALSE
|
||||
#define AT32_UART_USE_USART2 FALSE
|
||||
#define AT32_UART_USE_USART3 FALSE
|
||||
#define AT32_UART_USART1_DMA_PRIORITY 0
|
||||
#define AT32_UART_USART2_DMA_PRIORITY 0
|
||||
#define AT32_UART_USART3_DMA_PRIORITY 0
|
||||
#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define AT32_USB_USE_OTG1 TRUE
|
||||
#define AT32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define AT32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define AT32_WDG_USE_WDT FALSE
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue